Data collision avoidance circuit used in an image processing FIF

Details Data collision avoidance circuit used in an image processing FIF Data collision avoidance circuit used in an image processing FIF

1995-08-30

1998-02-17

Peng, John K.

Television

Image signal processing circuitry specific to television

With details of static storage device

348513, 348524, 348718, 386 91, H04N 5907

Patent

active

057196443

ABSTRACT:
A data collision avoidance circuit is utilized in a memory write control circuit of an image signal processing apparatus for preventing the write and read clocks of a FIFO memory from colliding. The circuit contains a write enable signal generating unit, a window pulse section set up unit, and a write enable signal control unit. The write enable signal generating unit generates a write enable signal in response to the write control odd/even field signal to write the data into the FIFO memory. The window pulse section set up unit generates a window pulse signal having a predetermined pulse width. The time interval of the predetermined pulse width is designed to be greater than a time interval during which write and read clocks of the FIFO memory can potentially collide, and the window pulse signal is generated in response to a read control odd/even field signal. The write enable signal control unit is designed to suppress the write enable signal generated by the write enable signal generating unit in response to a predetermined edge of the write control odd/even field signal during the window pulse signal. As a result, the collision of the write and read clocks is prevented.

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patent: 5646700 (1997-07-01), Park

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