Data clock regenerating apparatus

Details Data clock regenerating apparatus Data clock regenerating apparatus

2006-05-02

2006-05-02

Tran, Khanh (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000

Reexamination Certificate

active

07039149

ABSTRACT:
The present invention comprises a phase-locked loop which generates a first clock signal, and a phase-locked loop which generates a second clock signal. An upper limit value of a jitter transmission frequency in the phase-locked loop in which a jitter signal is transmitted to the first clock signal without being suppressed, is not less than an upper limit value of a jitter transmission frequency. An upper limit value of a jitter transmission frequency from the phase-locked loop to the phase-locked loop in which a jitter signal is transmitted to the second clock signal without being suppressed, is not more than an upper limit value of a jitter transmission frequency.

REFERENCES:
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patent: 6067335 (2000-05-01), Yamanoi et al.
patent: 6275553 (2001-08-01), Esaki
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patent: 6611175 (2003-08-01), Heymann
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patent: 6876651 (2005-04-01), Grohn
patent: SHO 63-136718 (1988-06-01), None
patent: HEI 3-258022 (1991-11-01), None
patent: 2000-3563 (2000-01-01), None
T.H. Lee, et al., A 155-MHz Clock Recovery Delay-and Phase-Locked Loop, IEEE Journal of Solid-state circuits, vol. 27, No. 12, Dec. 1992, pp. 1736-1747.

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