Data clock recovery PLL circuit using a windowed phase...

Details Data clock recovery PLL circuit using a windowed phase... Data clock recovery PLL circuit using a windowed phase...

1998-03-30

2001-07-10

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C370S503000

Reexamination Certificate

active

06259755

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a data and clock recovery PLL (phase locked loop) circuit which uses a Windowed Phase Comparator to extract a clock signal from its random input data in a data transmission system, or the like.
Phase locked loop circuits are very important components in data transmission systems. They are used in many different applications for example to eliminate skew between communication chips to recover a clock signal from random input data.
A conventional phase locked loop circuit includes a Gilbert Multiplier type phase detector and an emitter-coupled multivibrator VCO (voltage controlled oscillator). The conventional phase locked loop circuit can maintain stable lock for tens of consecutive identical bits without requiring a large external capacitor (to increase the RC time constant of the low-pass filter).
However, the phase locked loop circuit loses the lock when the number of consecutive identical bits reaches the hundreds. In addition, the phase locked loop circuit may fail to lock altogether when the input data frequency differs significantly from the phase locked loop's free-running frequency (or the initial oscillation frequency at time t=0) Moreover, the phase locked loop circuit suffers from harmonic lock.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a data and clock recovery PLL circuit which is stable in the operation.
It is another object of this invention to provide a data and clock recovery PLL circuit which can guarantee pull-in.
It is still another object of this invention to provide a data and clock recovery PLL circuit which has no problems with harmonic lock.
Other objects of this invention will become clear as the description proceeds.
On describing the gist of this invention, it is possible to understand that a data and clock recovery phase locked loop circuit extracts a clock signal from random input data.
According to a gist of this invention, a data and clock recovery phase locked loop circuit comprises a delay block for delaying the random input data to produce delayed random input data. A data transition detecting block detects transitions of the random input data to produce a window signal. A phase comparing block is connected to the delay block and compares phase of the delayed random input data with phase of a feedback signal to produce a phase compared signal representative of difference between the phase of the delayed random input data and the phase of a feedback signal. A charge pump block is connected to the phase comparing block and produces output voltage in response to the phase compared signal. A filter block is connected to the charge pump block to filter the output voltage into DC voltage. A voltage controlled oscillator is connected to the filter block to generate the clock signal which has a frequency depending on the DC voltage. A multiplexer block is connected to the voltage controlled oscillator, the data transition detecting block and the phase comparing block and selects one from a predetermined logical level and the clock signal to supply a selected signal to the phase comparing block as the feedback signal.
According to another gist of this invention, a data and clock recovery phase locked loop circuit comprises a delay block which delays the random input data to produce delayed random input data. A data transition detecting block detects transitions of the random input data to produce a window signal. A shifting block is connected to the data transition detecting block and shifts the window signal to produce a shifted window signal. A phase comparing block is connected to the delay block and the shifting block and compares phase of the delayed random input data with phase of the shifted window signal to produce a phase compared signal representative of difference between the phase of the delayed random input data and the phase of the shifted window signal. A charge pump block is connected to the phase comparing lock and produces output voltage in response to the phase compared signal. A filter block is connected to the charge pump block and filters the output voltage into DC voltage. A voltage controlled oscillator is connected to the filter block to generate the clock signal which has a frequency depending on the DC voltage.


REFERENCES:
patent: 5097489 (1992-03-01), Tucci
patent: 5212601 (1993-05-01), Wilson
patent: 5374860 (1994-12-01), Llewellyn
patent: 5446867 (1995-08-01), Young et al.
patent: 5557648 (1996-09-01), Ishihara
patent: 5900784 (1999-05-01), O'Sullivan
patent: 5986485 (1999-11-01), O'Sullivan
W.D. Llewellyn, M.M.H. Wong, G.W. Tietz, P.A. Tucci, “High-Speed Data Recovery”,IEEE International Solid-State Circuits Conference, 1998.

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