Data clock generator, data clock generating method, and...

Details Data clock generator, data clock generating method, and... Data clock generator, data clock generating method, and...

2000-01-07

2003-12-30

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C710S058000

Reexamination Certificate

active

06671343

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data clock generator and a data clock generating method that generate data clocks of a plurality of data samples at least from data packets comprised of the data samples and time stamps smaller in number than the number of the data samples, and a storage medium therefor.
2. Prior Art
When a plurality of data samples are transmitted in packets, time stamps smaller in number than the number of the data samples are added to the data samples to reduce the amount of data of the packets. For instance, in audio data packets conforming to the standard IEEE 1394, a single time stamp (SYT) is attached to eight samples (or sixteen samples) of audio data, to form packet data transmitted from a transmitting node to a receiving node, as shown in FIG.
1
.
FIG. 2
shows part of the arrangement of a conventional IEEE 1394 interface at the receiving node.
In
FIG. 2
, audio data packets sent from the transmitting node are separated into time stamp portions and data sample portions, and stored in an SYT receiving FIFO (First-In First-Out) memory
51
and an audio data receiving FIFO memory
52
, respectively. Time-sequential time stamps stored in the SYT receiving FIFO memory
51
are sequentially delivered in the order of older ones in predetermined timing to a time stamp register
53
for temporary storage, and then inputted to one input terminal of a comparator
55
. Since only one time stamp is attached to every eight samples, the frequency of generation of time stamps corresponds to one eighth of the frequency Fs of a sampling clock signal (hereinafter referred to as the word clock”) for reading (or generating) each data sample. The other input terminal of the comparator
55
receives an output from a system cycle timer
54
. The system cycle timer
54
generates a time count accurately representative of the frequency Fs of the word clock (hereinafter referred to as the “word clock frequency”). The comparator
55
compares each time stamp and each time count from the system cycle timer
54
, and delivers one pulse to one input terminal of a phase comparator
56
when the time stamp and the time count agree with each other. The phase comparator
56
, a low-pass filter (LPF)+voltage controlled oscillator (VCO)
57
, a 1
frequency divider
58
, and a ⅛ frequency divider
59
constitute a phase-locked loop (PLL) circuit. A sampling clock signal (this sampling clock signal is a clock signal for reading each bit of each data sample, and hence hereinafter referred to as the “bit clock”) generated by the LPF+VCO
57
, which has a frequency of n times the frequency Fs (the value n indicates the number of bits of bit data forming each data sample, and ranges e.g. from 64 to 256), is frequency-divided by the 1
frequency divider
58
, and thereby converted back into a sampling clock signal having the work clock frequency Fs which is then further frequency-divided by the ⅛ frequency divider
59
into a clock signal having a frequency of one eighth of the word clock frequency Fs, i.e. a time stamp-generating frequency Fs/8. The phase comparator
56
calculates a phase difference between the clock signal having the frequency Fs/8 and the clock signal having the frequency Fs/8 delivered from the comparator
55
, and generates a voltage commensurate with the phase difference, i.e. a voltage for controlling the VCO, which is then smoothed by the LPF, and applied to the VCO.
Thus, two kinds of accurate clock signals, i.e. the word clock having the frequency Fs and the bit clock having the frequency Fs×n, are generated, and delivered to a circuit at a subsequent stage.
In the conventional data clock generator, however, the PLL circuit generates the word clock and the bit clock with reference to the frequency which is one eighth of the word clock frequency Fs (one sixteenth of the same when each packet contains sixteen data samples). Therefore, if the number n of bits of each data sample is e.g. any one of 64 to 256, the PLL circuit is required to generate a clock signal having 512 to 2048 (or 1024 to 4096) times the frequency of the input signal (pulse signal from the comparator
55
). This necessitates the use of a high-precision PLL circuit, and hence increases the manufacturing cost of the data clock generator. Further, it is impossible to substantially reduce jitter in the clock signal generated, and achieve a sufficiently wide lock range of the PLL circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data clock generator and a data clock generating method which are capable of reducing burden on a PLL circuit and substantially reducing jitter in the generated data clock signal, as well as achieving a sufficiently wide lock range of the PLL circuit, and a storage medium therefor.
To attain the above object, according to a first aspect of the present invention, there is provided a data clock generator comprising a supply device that supplies data packet including at least a plurality of data samples and time stamps which are smaller in number than a number of the plurality of data samples, a time sample-generating device that generates time samples for respective ones of the data samples, from the time stamps of the data packets supplied from the supply device, and a PLL circuit that generates a data clock signal based on the time samples for the respective ones of the data samples generated by the time sample-generating device.
Preferably, the data clock signal comprises a word clock for reading each of the data samples, and a bit clock for reading each bit data of each of the data samples.
Preferably, each of the data packets comprises a plurality of data samples and one time stamp, each of the time samples being generated based on a difference between a time stamp of a present one of the data packets and a time stamp of an immediately preceding one of the data packets.
More preferably, each of the time samples is generated based on a quotient obtained by dividing the difference by the number of the plurality of data samples of each of the data packets.
Further preferably, each of the time samples is generated by sequentially adding a zero-fold value of the quotient to a n−1 fold value thereof to the time stamp of the immediately preceding one of the data packets.
To attain the above object, according to a second aspect of the invention, there is provided a storage medium storing a program that is executable by a computer, the program comprising a supply module for supplying data packets including at least a plurality of data samples and time stamps which are smaller in number than a number of the plurality of data samples, a time sample-generating module for generating time samples for respective ones of the data samples, from the time stamps of the data packets supplied by the supply module, and a data clock-generating module for causing a PLL circuit to generate a data clock signal based on the time samples for the respective ones of the data samples generated by the time sample-generating module.
To attain the above object, according to a third aspect of the invention, there is provided a data clock generating method comprising the steps of supplying data packets including at least a plurality of data samples and time stamps which are smaller in number than a number of the plurality of data samples, generating time samples for respective ones of the data samples, from the time stamps of the supplied data packets, and causing a PLL circuit to generate a data clock signal based on the time samples for the respective ones of the generated data


REFERENCES:
patent: 5815634 (1998-09-01), Daum et al.
patent: 5901149 (1999-05-01), Itakura et al.
patent: 6041090 (2000-03-01), Chen
patent: 6215742 (2001-04-01), Kuroda et al.
patent: 6381660 (2002-04-01), Ito
patent: 11-313107 (1999-09-01), None

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