Data classification in shared cache of multiple-core processor

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S141000, C711S144000

Reexamination Certificate

active

07571285

ABSTRACT:
In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.

REFERENCES:
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patent: 2002/0065992 (2002-05-01), Chauvel et al.
patent: 2005/0132140 (2005-06-01), Burger et al.
patent: 2006/0143384 (2006-06-01), Hughes et al.
U.S. Appl. No. 11/320,788, filed Dec. 30, 2005, entitled “Method and System For Proximity Caching In A Multiple-Core System” by Yen-Kuang Chen and Christopher J. Hughes.
Kattamuri Edanadham, Beng-Hong Lim, Pratap Pattnaik and Marc Snir, “PRISM: An Integrated Architecture for Scalable Shared Memory,” 1998, pp. 1-12.
Changkyu Kim, Doug Burger and Stephen W. Keckler, “An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches,” 2002, pp. 1-12.
Bradford M. Beckmann and David A. Wood, “Managing Wire Delay in Large Chip-Multiprocessor Caches,” 2004, pp. 1-12.
Michael Zhang and Krste Asanovié, “Victim Replication: Maximizing Capacity While Hiding Wire Delay in Tiled Chip Multiprocessors,” Jun. 2005, pp. 1-10.
Jichuan Chang and Gurindar S. Sohi, “Cooperative Caching For Chip Multiprocessors,” Jun. 17, 2006, pp. 1-12.

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