Data channel test apparatus and method thereof

Details Data channel test apparatus and method thereof Data channel test apparatus and method thereof

2011-03-22

2011-03-22

Beausoliel, Robert (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S712000

Reexamination Certificate

active

07913128

ABSTRACT:
A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.

REFERENCES:
patent: 4174536 (1979-11-01), Misunas et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4733376 (1988-03-01), Ogawa
patent: 4796231 (1989-01-01), Pinkham
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5132635 (1992-07-01), Kennedy
patent: 5136292 (1992-08-01), Ishida
patent: 5175819 (1992-12-01), Le Ngoc et al.
patent: 5185722 (1993-02-01), Ota et al.
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5280539 (1994-01-01), Yeom et al.
patent: 5365484 (1994-11-01), Cleveland et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5430735 (1995-07-01), Sauerwald et al.
patent: 5440694 (1995-08-01), Nakajima
patent: 5452259 (1995-09-01), McLaury
patent: 5473563 (1995-12-01), Suh et al.
patent: 5473566 (1995-12-01), Rao
patent: 5473577 (1995-12-01), Miyake et al.
patent: 5526311 (1996-06-01), Kreifels et al.
patent: 5579272 (1996-11-01), Uchida
patent: 5596724 (1997-01-01), Mullins et al.
patent: 5602780 (1997-02-01), Diem et al.
patent: 5636342 (1997-06-01), Jeffries
patent: 5671178 (1997-09-01), Park et al.
patent: 5691949 (1997-11-01), Hively et al.
patent: 5721840 (1998-02-01), Soga
patent: 5740379 (1998-04-01), Hartwig
patent: 5761146 (1998-06-01), Yoo et al.
patent: 5771199 (1998-06-01), Lee
patent: 5777488 (1998-07-01), Dryer et al.
patent: 5802006 (1998-09-01), Ohta
patent: 5818785 (1998-10-01), Ohshima
patent: 5828899 (1998-10-01), Richard et al.
patent: 5835935 (1998-11-01), Estakhri et al.
patent: 5859809 (1999-01-01), Kim
patent: 5872994 (1999-02-01), Akiyama et al.
patent: 5896400 (1999-04-01), Roohparvar et al.
patent: 5900021 (1999-05-01), Tiede et al.
patent: 5913928 (1999-06-01), Morzano
patent: 5926422 (1999-07-01), Haukness
patent: 5937425 (1999-08-01), Ban
patent: 5941974 (1999-08-01), Babin
patent: 5959930 (1999-09-01), Sakurai
patent: 5995417 (1999-11-01), Chen et al.
patent: 6002638 (1999-12-01), John
patent: 6049901 (2000-04-01), Stock et al.
patent: 6085290 (2000-07-01), Smith et al.
patent: 6091660 (2000-07-01), Sasaki et al.
patent: 6107658 (2000-08-01), Itoh et al.
patent: 6144576 (2000-11-01), Leddige et al.
patent: 6148364 (2000-11-01), Srinivasan et al.
patent: 6178135 (2001-01-01), Kang
patent: 6185708 (2001-02-01), Sugamori
patent: 6295618 (2001-09-01), Keeth
patent: 6304921 (2001-10-01), Rooke
patent: 6317350 (2001-11-01), Pereira et al.
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6438064 (2002-08-01), Ooishi
patent: 6442098 (2002-08-01), Kengeri
patent: 6535948 (2003-03-01), Wheeler et al.
patent: 6584303 (2003-06-01), Kingswood et al.
patent: 6594183 (2003-07-01), Lofgren et al.
patent: 6601199 (2003-07-01), Fukuda et al.
patent: 6611466 (2003-08-01), Lee et al.
patent: 6658582 (2003-12-01), Han
patent: 6680904 (2004-01-01), Kaplan et al.
patent: 6715044 (2004-03-01), Lofgren et al.
patent: 6732221 (2004-05-01), Ban
patent: 6754807 (2004-06-01), Parthasarathy et al.
patent: 6763426 (2004-07-01), James et al.
patent: 6799133 (2004-09-01), McIntosh et al.
patent: 6807103 (2004-10-01), Cavaleri et al.
patent: 6816933 (2004-11-01), Andreas
patent: 6850443 (2005-02-01), Lofgren et al.
patent: 6853557 (2005-02-01), Haba et al.
patent: 6853573 (2005-02-01), Kim et al.
patent: 6928501 (2005-08-01), Andreas et al.
patent: 6930936 (2005-08-01), Santin
patent: 6938188 (2005-08-01), Kelleher
patent: 6944697 (2005-09-01), Andreas
patent: 6950325 (2005-09-01), Chen
patent: 6961882 (2005-11-01), Manfred et al.
patent: 6967874 (2005-11-01), Hosono
patent: 6978402 (2005-12-01), Hirabayashi
patent: 7024605 (2006-04-01), Sera et al.
patent: 7073022 (2006-07-01), El-Batal et al.
patent: 2002/0188781 (2002-12-01), Schoch et al.
patent: 2004/0001380 (2004-01-01), Becca et al.
patent: 2004/0019736 (2004-01-01), Kim et al.
patent: 2004/0024960 (2004-02-01), King et al.
patent: 2004/0039854 (2004-02-01), Estakhri et al.
patent: 2004/0199721 (2004-10-01), Chen
patent: 2004/0230738 (2004-11-01), Lim et al.
patent: 2005/0015213 (2005-01-01), Somervill et al.
patent: 2005/0105350 (2005-05-01), Zimmerman
patent: 2005/0160218 (2005-07-01), See et al.
patent: 2005/0213421 (2005-09-01), Polizzi et al.
patent: 2006/0050594 (2006-03-01), Park
patent: 2006/0107186 (2006-05-01), Cowell et al.
patent: 2007/0022349 (2007-01-01), Bertocelli et al.
patent: 2009/0006837 (2009-01-01), Rothman et al.
patent: 0350538 (1993-12-01), None
patent: 0588507 (1998-01-01), None
International Application No. PCT/CA2008/002051: International Search Report dated Mar. 9, 2009, p. 2.
Samsung Electronics Co. LTD, “256M×8 Bit / 128 M×16 Bit / 512M×8 Bit NAND Flash Memory”, K9K4GO8U1M, May 6, 2005, pp. 1-41.
Toshiba, “2GBIT (256M×8 Bits) CMOS NAND E2PROM”, TH58NVG1S3AFT05, May 19, 2003, pp. 1-32.
Amtel Corp., “High Speed Small Sectored SPI Flash Memory”, pp. 1-22, 2006.
64 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI, Spansion, pp. 1-22 (2006).
King, et al., “Communicating with Daisy Chained MCP42XXX Digital Potentiometers”, Microchip AN747, pp. 1-8, 2001.
Intel Corporation, “Intel® Advanced+ Boot Block Flash Memory (C3)”, May 2005, pp. 1-72.
M-Systems Flash Disk Pioneers LTD., “DiskOnChip H1 4Gb (512MByte) and 8Gb (1 GByte) High Capacity Flash Disk with NAND and ×2 Technology”, Data Sheet, Rev. 0.5 (Preliminary), pp. 1-66, 2005.
Tal, A., “Guidelines for Integrating DiskOnChip in a Host System”, AP-DOC-1004, Rev. 1.0, M-Systems Flash Pioneers Ltd., pp. 1-15, 2004.
Samsung Electronics Co. Ltd, OneNAND4G(KFW4G16Q2M-DEB6), OneNAND2G(KFH2G16Q2M-DEB6), OneNAND1G(KFW1G16Q2M-DEB6) Flash Memory, OneNAND™ Specification Ver. 1.2, pp. 1-125, Dec. 23, 2005.
Kennedy, J., et al., “A 2Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable Memory Subsystems”, ISSCC 2004/Session 1/DRAM/11.8, IEEE International Solid-State Circuits Conference, Feb. 15-19, 2004, vol. 1, pp. 214-523.
Kim, Jae-Kwan, et al., “A 3.6Gb/s/pin Simultaneous Bidirectional (SBD) I/O Interface for High-Speed DRAM”, ISSCC 2004/Session 22/DSL and Multi-Gb/s I/O 22.7, IEEE International Solid-State Circuits Conference Feb. 15-19, 2004, vol. 1, pp. 414-415.
“HyperTransport TM I/O Link Specification”, Revision 2.00, Document No. HTC20031217-0036-00, Hypertransport Technology Consortium, pp. 1-325, 2001.
“IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)”, IEEE Std. 1596.4-1996, The Institute of Electrical Electronics Engineers, Inc., pp. i-91, (Mar. 1996).
Oshima, et al., “High-Speed Memory Architectures for Multimedia Applications”, Circuits & Devices, IEEE 8755-3996/97, pp. 8-13, Jan. 1997.
Gjessing, S., et al., “RamLink: A High-Bandwidth Point-to-Point Memory Architecture”, Proceedings CompCom 1992, IEEE 0-8186-2655-0/92, pp. 328-331, Feb. 24-28, 1992.
Gjessing, S., et al., “Performance of the RamLink Memory Architecture”, Proceedings of the Twenty-Seventh Annual Hawaii International Conference on System Sciences, IEEE 1060-3425/94, pp. 154-162, Jan. 1994.
Gjessing, S., et al., “A RAM Link for High Speed”, Special Report/Memory, IEEE Spectrum, pp. 52-53, Oct. 1992.
Diamond, S.L., “SyncLink: High: High-speed DRAM for the Future”, Mic

Affiliated with

Also associated with

Rating

Data channel test apparatus and method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data channel test apparatus and method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data channel test apparatus and method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2755986