Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-11-01
2005-11-01
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C340S010100, C340S572300, C235S436000, C235S375000
Reexamination Certificate
active
06961829
ABSTRACT:
A data carrier (2) or an integrated circuit (41) for a data carrier (2) comprises a memory (54) which is designed to store intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state of the data carrier (2) or the integrated circuit (41) and comprises a memory control device (51), which after the occurrence of information significant for intermediate operating states ensures that this intermediate operating state information is stored in the memory (54) and comprises a control device (51), which—after the detection of the non-existence of the supply voltage (V) required for faultless operation during execution of a communication sequence interrupted by this non-existence and the subsequent detection of the re-existence of the supply voltage (V)—ensure that the data carrier (2) or the integrated circuit (41) is controlled in an intermediate operating state for which intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory (54) is significant.
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“ISO/IEC 18000-3-1: Automated Identification—Radio Frequency Identification for Item Management—Communications and Interfaces—Part 3: Physical Layer, Anti collision System and Protocol Values at 13:56 MHz mode 1”, © ISO 1999, p. i-99.
ISO/IEC 18000-3-5 of Mar. 1, 2002 with reference No. ISO/WD 18000-3-v40-5.
Peugh Brian R.
Stroud Adam L.
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