Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-08-31
1999-01-12
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711204, 711213, 711126, 395383, G06F 938
Patent
active
058601040
ABSTRACT:
A data cache configured to perform store accesses in a single clock cycle is provided. The data cache speculatively stores data within a predicted way of the cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete. If the way prediction is incorrect, then the captured data is restored to the predicted way. If the store access hits in an unpredicted way, the store data is transferred into the correct storage location within the data cache concurrently with the restoration of data in the predicted storage location. Each store for which the way prediction is correct utilizes a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The present data cache is therefore suitable for high frequency superscalar microprocessors.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4901233 (1990-02-01), Liptay
patent: 4905141 (1990-02-01), Brenza
patent: 4912626 (1990-03-01), Fiacconi
patent: 5091851 (1992-02-01), Shelton et al.
patent: 5148538 (1992-09-01), Celtruda et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5228134 (1993-07-01), MacWilliams et al.
patent: 5235697 (1993-08-01), Steely, Jr. et al.
patent: 5269017 (1993-12-01), Hayden et al.
patent: 5418922 (1995-05-01), Liu
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5495590 (1996-02-01), Comfort et al.
patent: 5509119 (1996-04-01), La Fetra
patent: 5530958 (1996-06-01), Agarwal et al.
patent: 5564034 (1996-10-01), Miyake
patent: 5584009 (1996-12-01), Garibay, Jr. et al.
patent: 5590352 (1996-12-01), Zuraski, Jr. et al.
patent: 5596740 (1997-01-01), Quattromani et al.
patent: 5603047 (1997-02-01), Caulk, Jr.
IBM Technical Disclosure Bulletin, vol. 30, No. 10, Mar. 1988, New York, US, XP002029778, "Fast Cache Access Based on Most Recently Used Hits," pp. 1-4.
Intel, "Chapter 2: Microprocessor Architecture Overview," pps. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
Hattangadi Rajiv M.
Witt David B.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Merkel Lawrence J.
Peikari J.
Swann Tod R.
LandOfFree
Data cache which speculatively updates a predicted data cache st does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data cache which speculatively updates a predicted data cache st, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data cache which speculatively updates a predicted data cache st will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1525121