Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-05-30
2006-05-30
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S124000, C711S134000
Reexamination Certificate
active
07055003
ABSTRACT:
A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches. The L2 cache can be forced to victimize cache lines, by setting tag bits for the cache lines to a value that misses in the L2 cache (e.g., cache-inhibited space). With the eviction mechanism of the cache placed in a direct-mapped mode, the address misses will result in eviction of the cache lines, thereby flushing them to the L3 cache.
REFERENCES:
patent: 5895488 (1999-04-01), Loechel
patent: 5974507 (1999-10-01), Arimilli et al.
patent: 6480975 (2002-11-01), Arimilli et al.
patent: 6493801 (2002-12-01), Steely et al.
patent: 2002/0112129 (2002-08-01), Arimilli et al.
Cargnoni Robert Alan
Guthrie Guy Lynn
Helterhoff Harmony Lynn
Reick Kevin Franklin
Elmore Reba I.
International Business Machines - Corporation
Musgrove Jack V.
Salys Casimer K.
LandOfFree
Data cache scrub mechanism for large L2/L3 data cache... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data cache scrub mechanism for large L2/L3 data cache..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data cache scrub mechanism for large L2/L3 data cache... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3535030