Data cache prefetching under control of instruction cache

Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address

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711204, 711123, 711126, 711125, G06F 932

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active

057847118

ABSTRACT:
A data prefetching arrangement for use between a computer processor and a main memory. The addresses of data to be prefetched are calculated by decoding instructions which have been prefetched by decoding prefetched instructions, the instructions having been in accordance with an intelligent prefetching scheme. The processor registers have two sections for respective access by the processor and a prefetch controller. The instruction registers may also contain an additional counter field which indicates the number of instruction cycles which must be executed before the register may be reliably utilized for prefetching data.

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IBM Technical Disclosure Bulletin vol. 15, No. 4, Sep. 1972, NY, USA pp. 1100-1101, "Storage Herarchy Control System".
IBM Technical Disclosure Bulletin vol. 32, No. 7, Dec. 1989, NY, USA pp. 274-275, "Cache Miss Leading Edge Processing".

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