Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-08-09
2011-08-09
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711SE12072, C345S557000
Reexamination Certificate
active
07996621
ABSTRACT:
According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.
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Brown Jeffrey Douglas
Hoover Russell Dean
Mejdrich Eric Oliver
Valk Kenneth Michael
Bragdon Reginald G
International Business Machines - Corporation
Patterson & Sheridan LLP
Sadler Nathan
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