Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-05-06
1998-10-27
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711137, 711120, G06F 1208
Patent
active
058290281
ABSTRACT:
A cache is provided which prefetches data words associated with a particular addressing mode. When a data word is accessed in response to the execution of an instruction, the data word is discarded by the cache. Data which is accessed in a use-once fashion (such as DSP data, for example) may be thereby available with cache-hit memory access times instead of main memory access times. The present cache prefetches data words spaced at regular or irregular intervals, wherein the interval is specified by the addressing mode of the instruction. Multiple words within a data stream may be successfully prefetched. The cache described herein may be incorporated into a microprocessor having a conventional cache as well. Data which is indicated to be used once may be stored in the present cache, while data exhibiting locality may be stored in the conventional cache. Data which exhibits locality is thereby retained within the cache system when use-once data is accessed.
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Lynch Thomas W.
Yard Christopher J.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Lee Felix B.
Swann Tod R.
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