Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-03-01
2003-08-05
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C345S552000, C345S557000
Reexamination Certificate
active
06604175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to storing and retrieving data. Specifically, the present invention relates to storing data in a cache and retrieving data from the cache.
2. Description of the Related Art
In computer graphics, existing texture-rendering techniques map a pixel on a screen (typically using screen coordinates (x, y)) to a polygon, such as a triangle, on a surface in a viewing plane (typically using geometric or surface coordinates (s, t)). The polygon is rasterized into a plurality of smaller pieces called fragments. Each polygon may have information, such as color and/or a normal vector, associated with each vertex of the polygon. To assign a texture (i.e., a color pattern or image, either digitized or synthesized) to a fragment, the fragment is mapped onto a texture map (typically using texture coordinates (u, v)). A texture map represents a type of image, such as stripes, checkerboards, or complex patterns that may characterize natural materials. Texture maps are stored in a texture memory. A texture map comprises a plurality of texels. A texel is the smallest graphical element in a 2-D texture map used to render a 3-D object. A texel represents a single color combination at a specific position in the texture map.
Each texture map has a plurality of associated MIP (multum in parvo) maps, which are abbreviated versions of a full texture map. One of the MIP maps may be selected to provide a suitable resolution for the fragment of the polygon being rasterized. Several techniques exist to interpolate the desired color information from one or more MIP levels. These texel selection techniques are known technology. The final texture color derived from the selected MIP map is applied onto the fragment. The applied texture may be blended with a color already associated with the fragment or polygon.
In a traditional graphics rendering pipeline/architecture, a texturing unit will access a texture memory via a texture cache. This traditional architecture treats the texture cache as a single large cache or lookup table created from most of the memory available in the texture cache. A texture memory controller passes new texel data packets from all the texture maps to the single texture cache. Any texel data from any texture map may overwrite texel entries from other maps. There are no provisions for dealing with texel data packets that are frequently re-used compared to texel data packets that are used only intermittently or infrequently. A frequently re-used texel data packet may be written over, reloaded again, written over and then reloaded again repeatedly. The operation of having a single cache handle texel data from many texture maps is inefficient.
SUMMARY OF THE INVENTION
A data cache and methods of organizing a data cache are provided in accordance with the present invention. In one embodiment, the methods of organizing a data cache are applied to a texture cache in a graphics rendering system. The texture cache is split into a plurality of individual, independently cached areas (ICAs), where each ICA is assigned to store the texel data packets associated with a particular texture. Each ICA has a texture usage indicator that indicates the frequency of read requests for texel data packets stored in that ICA. A particular ICA with texel data packets that are not frequently requested will be assigned to store texel data packets for another texture. An ICA with frequently used texels will remain available to the rendering engine. Thus, the texture cache according to the present invention is more efficient than a traditional texture cache.
Also, a texture ID may be removed from each texel data packet before the packet is stored in an ICA because each ICA is dedicated to store texel data packets for one texture. By storing texel data packets without a texture ID, more cache memory in the ICA is available to store other texel data packets.
In another embodiment, the methods of organizing a data cache are applied to a central processing unit (CPU) cache. According to the present invention, the CPU cache has a plurality of individual caches that store different types of CPU processes, such as threads or tasks, instead of texel data packets.
One aspect of the invention relates to a memory system comprising a memory, a memory controller and a cache. The memory is configured to store a plurality of data packets, which are associated with a plurality of data types. The memory controller is coupled to the memory. The controller is configured to receive requests for data packets from a processing unit and pass requested data packets from the memory to the processing unit. The cache is coupled to the memory controller. The cache comprises a plurality of independently cached areas (ICAs). The memory controller is configured to pass requested data packets from the memory to the cache. The memory controller is configured to pass requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller. The memory controller is configured to assign each ICA in the cache to store data packets associated with one data type. Each ICA is associated with a data usage indicator. The memory controller is configured to (1) increment the data usage indicator of an ICA for each data packet passed from that ICA to the processing unit in response to a subsequent data packet request and (2) decrement the data usage indicators of other ICAs.
Another aspect of the invention relates to a method of storing data. The method comprises storing a plurality of data packets in a memory, where the data packets are associated with a plurality of data types; receiving requests for data packets from a processing unit with a memory controller coupled to the memory and passing requested data packets from the memory to the processing unit; passing requested data packets from the memory to a cache and passing requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller, where the cache comprises a plurality of independently cached areas; assigning each independently cached areas in the cache to store data packets associated with one data type, where each independently cached area is associated with a data usage indicator; incrementing the data usage indicator of an independently cached area for each data packet passed from that independently cached area to the processing unit in response to a subsequent data packet request; and decrementing the data usage indicators of other independently cached areas.
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Meyer Fortkort & Williams, PC
Moazzami Nasser
Sony Corporation
Williams Esq. Karin L.
Yoo Do Hyun
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