Data bus sense amplifier circuit

Details Data bus sense amplifier circuit Data bus sense amplifier circuit

2001-10-18

2004-03-23

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S208000

Reexamination Certificate

active

06711079

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data bus sense amplifier circuit, and in particular to an improved data bus sense amplifier circuit for reducing noise generated during its read mode operation and increasing a read margin in a VLSI semiconductor DRAM device into which it is incorporated.
2. Description of the Background Art
FIG. 1
(Prior Art) is a circuit diagram of a conventional data bus sense amplifier circuit. The conventional data bus sense amplifier circuit comprises a precharge unit
10
, an amplifying unit
20
and a switching unit
30
.
The precharge unit
10
includes PMOS transistors P
1
and P
2
which switch according to a state of a sense amp enable signal RSASEL input in the form of a pulse signal to generate a precharge voltage. A PMOS transistor P
3
equalizes output terminals of the precharge unit
10
.
The amplifying unit
20
includes NMOS transistors N
1
and N
2
and PMOS transistors P
4
and P
5
connected in a cross-coupled structure. NMOS transistors N
3
and N
4
receive data signals through their respective gate terminals from data bus lines LIO and LIOb. Accordingly, a data bus sense amp switches NMOS transistors N
6
and N
7
by sensing the data from the data bus lines LIO and LIOb, thereby controlling bit line read signals BL_RD and BL_RDb.
The switching unit
30
includes an NMOS transistor N
5
. When the sense amp enable signal RSASEL is enabled, the switching unit
30
grounds a leakage current generated in the amplifying unit
20
to a ground terminal.
In this conventional data bus sense amplifier circuit, the sense amp must maintain an identical power supply voltage state in a precharge mode, and sense the data from the data bus lines LIO and LIOb rapidly when the sense amp enable signal RSASEL is enabled in a read mode.
The conventional data bus sense amplifier circuit has some operational disadvantages including the following:
First, the conventional data bus sense amp requires an extended period of time to completely enable a pulse of the sense amp enable signal to a high level due to noise generated by a peripheral power source line. Accordingly, the NMOS transistor N
5
of the switching unit
30
is not rapidly turned on, thus reducing a sensing speed.
Second, the conventional data bus sense amp cannot maintain a complete low state of the sense amp enable signal RSASEL due to noise generated by a peripheral line before a read operation, especially the power supply line.
In this case, the sense amp enable signal RSASEL is unnecessarily enabled at a high level due to noise of a sense amp enable signal line, thereby generating the leakage current in the NMOS transistor N
5
connected to an input line of the sense amp enable signal RSASEL.
That is, when data opposite to the existing data is inputted to the data bus lines LIO and LIOb in an actual read operation, the leakage current is generated from one of the NMOS transistors N
3
and N
4
of the amplifying unit
20
to the NMOS transistor N
5
, thereby causing data failure.
Moreover, in the case that all the lines are connected to a power supply voltage in a precharge period, the leakage current is continuously generated, which results in high power consumption.
SUMMARY OF THE INVENTION
Among the inventions described and claimed in this patent document, there is an object in providing a data bus sense amplifier circuit which rapidly turn on a switching unit when a sense amp enable signal is enabled thereby improving sensing speed than that of conventional data bus sense amplifiers.
There is also an object in providing a data bus sense amplifier circuit which can prevent the flow of a leakage current generated in a switching unit by connecting switching transistors in series to the switching unit for grounding a sensing current, when a sense amp enable signal is disabled.
These inventions are provided by utilizing novel circuit arrangements. In one respect, our data bus sense amplifier circuit includes an amplifying unit, a precharge unit and a switching means. An amplifying unit having a cross-coupled structure for sensing data of a data bus line according to a sense amp control signal. A precharge unit provides a precharge voltage to the amplifying unit according to a sense amp enable signal. A switching means has a transmission gate at an input terminal of the sense amp enable signal to ground a sensing voltage of the amplifying unit when the sense amp enable signal is enabled.
According to one aspect of the inventions, a data bus sense amplifier circuit includes an amplifying unit, a precharge unit and a switching means. An amplifying unit having a cross-coupled structure for sensing data of a data bus line according to a sense amp control signal. A precharge unit provides a precharge voltage to the amplifying unit according to a sense amp enable signal. A switching means maintains a disabled state of the sense amp enable signal by connecting a plurality of switching elements in series to an input terminal of the sense amp enable signal.
According to another aspect of the inventions, a data bus sense amplifier circuit includes an amplifying unit, a precharge unit and a switching means. An amplifying unit having a cross-coupled structure for sensing data of a data bus line according to a sense amp control signal. A precharge unit provides a precharge voltage to the amplifying unit according to a sense amp enable signal. A switching means is turned on for grounding a sensing voltage of the amplifying unit when the sense amp enable signal is enabled and for maintaining a disabled state of the sense amp enable signal, operating as a resistance element, when the sense amp enable signal is disabled.


REFERENCES:
patent: 4694205 (1987-09-01), Shu et al.
patent: 5831897 (1998-11-01), Hodges
patent: 5949706 (1999-09-01), Chang et al.

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