Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
2011-07-19
2011-07-19
Rinehart, Mark (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C711S154000, C713S401000, C713S600000
Reexamination Certificate
active
07984214
ABSTRACT:
In a data bus with asynchronous data transmission via a clock and a data line, the transmitted data are ascertained by sampling with a multiple of the data rate of the data bus. Sampling is done in this case with a clock which is not synchronous with the asynchronous clock of the data bus. For avoiding interferences which develop due to the unnecessary operation of the interface circuit with a high frequency clock when no data are currently transmitted, a control circuit is provided for detecting the beginning and the end of a data transmission. Only at the beginning of a data transmission, the interface circuit will be supplied with the required clock. After the end of the data transmission, the clock for the interface circuit will be switched off again. The control circuit is preferably designed as a state machine which reacts, without the need for clock signals, to the states on the data and clock line of the data bus.
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Search Report Dated Apr. 25, 2007.
DE Search Report.
Daley Christopher A
Navon Jeffrey M.
Rinehart Mark
Shedd Robert D.
Thomson Licensing
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