Computer graphics processing and selective visual display system – Computer graphics display memory system – For storing compressed data
Reexamination Certificate
1998-10-13
2001-11-20
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Computer graphics display memory system
For storing compressed data
C382S232000, C382S233000, C382S235000, C382S251000, C348S390100, C348S405100
Reexamination Certificate
active
06320590
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a bus compression device for reducing or compressing the number of bit signals representing parallel data. This invention is also directed to a bus decompression device for extending the number of bit signals representing compressed parallel data. Further, this invention relates to a data interface employing a bus compressing method and to a liquid crystal display using the data interface.
2. Description of the Prior Art
Since the transmission of audio information many years ago, higher band or capacity signals containing text information, video information and the like have been transmitted using various bus interfaces to transmit signals containing substantially more information than the audio information. The text information, video information and the like occupy a high frequency band and require many transmission lines. As the frequency band for the information and the number of transmission lines increase, an electromagnetic interference (EMI) increases between the transmission lines. The EMI problem is common in a data bus. In order to reduce the EMI in the transmission line, line matchers have been usually added to the transmission line. However, such line matcher complicates a wiring structure of the transmission line and limits the system design.
For example, as shown in
FIG. 1
, a computer system employing a liquid crystal display (LCD) includes various kinds of couplers LM
1
to LM
5
provided between a video card
12
in a computer body
10
and data driver integrated circuits D-ICs
24
in an LCD
20
. Specifically, twenty-eight first line matchers LM
1
corresponding to a 18-bit first bus
11
and a 10-bit first control bus
13
are arranged between the video card
12
and a first cable connector
16
. Eighteen second matchers LM
2
and ten third matchers LM
3
respectively corresponding to a 18-bit second bus and a 10-bit control bus
23
are arranged between a second cable connector
18
and a controller
26
. Finally, thirty-six fourth line matcher LM
4
and seven fifth line matchers LM
5
corresponding to a thirty-six bit third bus
35
and a seven bit third control bus are arranged between the controller
26
and the D-ICs
24
.
As shown in
FIG. 2
, each line matcher LM
1
includes a resistor R
1
, a capacitor C
1
and an inductor L
1
which are connected in the T shape. As shown in
FIG. 3
, each line matcher LM
2
includes a resistor R
1
, a capacitor C
2
and two inductors L
2
and L
3
. As shown in
FIG. 4
, each line matcher LM
3
includes an inductor L
4
and a resistor R
3
. Each line matcher LM
4
includes a resistor R
4
and a capacitor C
3
as shown in FIG.
5
. The line matcher LM
5
includes an inductor L
5
, a resistor R
5
and a capacitor C
4
.
The matchers LM
1
to LM
5
match an impedance and eliminate high frequency and/or low frequency components, thereby suppressing an occurrence of EMI. As a result, the data passing through the flexible printed circuit (FPC) cable
16
and the first to third data buses
11
,
21
and
25
and the clock and timing signals transmitted through the FPC cable
16
and the first to third control buses
13
,
23
and
27
are not influenced by the EMI.
As described above, in the conventional computer system having a number of line matchers installed in the transmission line extending from the video card in the computer body to the D-ICs in the LCD, the configuration thereof becomes complicated and the design thereof is limited due to the line matchers. Also, the conventional computer system requires as many transmission lines as the number of data bits.
Furthermore, as the number of picture elements or pixels in the liquid crystal panel increase above the XGA format, the data bus installed between the controller and the D-ICs must have a dual structure due to a response speed of the D-ICs. In this case, the circuit configuration of the LCD having a wiring structure becomes more complicated and a die arranged with the D-ICs must be enlarged.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a bus compressing apparatus which is capable of compressing data in such a manner to suppress an EMI as well as to simplify a data bus.
Further object of the present invention is to provide a bus decompressing apparatus for decompressing the data compressed by the above-mentioned compressing method.
Another object of the present invention is to provide an interfacing unit that is suitable for reducing the number of transmission lines.
Still another object of the present invention is to provide a liquid crystal display wherein the wiring structure and circuit configuration thereof are simplified.
In order to achieve these and other objects of the invention, a bus compressing apparatus according to one aspect of the present invention includes at least two bit lines for receiving a bit data stream each; at least two voltage control means, each provided in the at least two bit lines, for changing voltage levels on each line into a ratio different each other; and adder means for adding the voltage levels changed by the at least voltage control means to generate and transfer an analog signal.
A bus decompressing apparatus according to another aspect of the present invention includes means for receiving a single of analog signal in which at least two parallel bit data are compressed; quantizing means for quantizing the analog signal from the receiving means; and coding means for coding the quantized analog signal to reconstruct the at least two bit parallel data.
A data interfacing apparatus according to still another aspect of the present invention includes bus compressing means for compressing at least two bit parallel data into a single of analog signal; and bus decompressing means, being installed in a data terminal, for decompressing for decompressing the analog signal from the data compressing means into the at least two bit parallel data.
A liquid crystal display according to still another aspect of the present invention includes driver integrated circuits for divisionally driving a liquid crystal panel with at least two bit video data; signal input means for inputting a single analog signal, in which the at least two video data are compressed, from the exterior; and bus decompressing means for decompressing the analog signal from the signal input means into the at least two bit video data and for supplying the decompressed video data to the driver integrated circuits.
REFERENCES:
patent: 4348659 (1982-09-01), Fujimori et al.
patent: 5081450 (1992-01-01), Lucas
patent: 5115450 (1992-05-01), Arcuri
patent: 5408498 (1995-04-01), Yoshida
patent: 5585796 (1996-12-01), Svensson et al.
patent: 5930398 (1999-07-01), Watney
patent: 6064771 (2000-05-01), Migdal et al.
patent: 6078361 (2000-06-01), Reddy
patent: 49-17115 (1974-02-01), None
patent: 60-239141 (1985-11-01), None
patent: 61-281734 (1986-12-01), None
patent: 64-14631 (1989-01-01), None
patent: 1-243623 (1989-09-01), None
patent: 3-258025 (1991-11-01), None
patent: 5-14420 (1993-01-01), None
Kovalick Vincent E.
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Shalwala Bipin
LandOfFree
Data bus compressing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data bus compressing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data bus compressing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2587273