Data bus clamp circuit for a semiconductor memory device

Details Data bus clamp circuit for a semiconductor memory device Data bus clamp circuit for a semiconductor memory device

1991-11-26

1993-11-09

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Including signal clamping

365204, 365208, 36523006, 36523008, 365233, G11C 700

Patent

active

052609049

ABSTRACT:
A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

REFERENCES:
patent: 4494222 (1985-01-01), White et al.
patent: 4636986 (1987-01-01), Pinkham
patent: 4809230 (1989-02-01), Konishi et al.
patent: 4961168 (1990-10-01), Tran
patent: 4985868 (1991-01-01), Nakano et al.
patent: 5083296 (1992-01-01), Hara et al.
patent: 5091886 (1992-02-01), Miyawaki et al.

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