Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-07-26
2011-07-26
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07987408
ABSTRACT:
In a data processing and buffering method, at least one read cycles are asserted to obtain at least one data, respectively, wherein each of the data includes at least one sub data and each data is specified with an address pointer and an enable bit array. When a certain sub data is received, the corresponding bit of the enable bit array is enabled. The corresponding sub data of the enabled bit is indicated by the address pointer.
REFERENCES:
patent: 5553265 (1996-09-01), Abato et al.
patent: 6381532 (2002-04-01), Bastian et al.
patent: 2004/0103262 (2004-05-01), Glossner et al.
Kirton & McConkie
Lamarre Guy J
VIA Technologies Inc.
Witt Evan R.
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