Data buffer prefetch apparatus and method

Details Data buffer prefetch apparatus and method Data buffer prefetch apparatus and method

1996-07-01

1998-12-29

Kuntz, Curtis A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395383, 39542103, 395375, 711213, 711123, 711118, G06F 1312, G06F 1314

Patent

active

058549110

ABSTRACT:
A prefetch apparatus optimizes bandwidth in a computer network by prefetch accessing data blocks prior to their demand in an ATM network thereby effectively reducing memory read latency. The method of the preferred embodiment includes the steps of: 1) computing a prefetch address of a next sequential data block given an address of a requested data block; 2) comparing a current request address against a previously computed prefetch address; and 3) generating a hit/miss indication corresponding to whether the current request address matches the previously computed prefetch address.

REFERENCES:
patent: 4157587 (1979-06-01), Joyce et al.
patent: 5345560 (1994-09-01), Miura et al.
patent: 5553254 (1996-09-01), Berstis et al.
patent: 5602853 (1997-02-01), Ben-Michael et al.
patent: 5715425 (1998-02-01), Goldman et al.

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