Data buffer for programmable memory

Details Data buffer for programmable memory Data buffer for programmable memory

1998-11-03

2001-07-03

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

C710S052000, C711S154000

Reexamination Certificate

active

06256681

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data buffer and method, and in particular, to a data buffer and method for using same that interfaces input/output buffers in a multi-state programmable memory.
2. Background of the Related Art
Generally, programmable memory devices such as a mass storage flash memory have less than 8 (i.e., 1 byte) input/output pins, and internally have dozens of sense amplifiers. The input/output pins transmit data by being synchronized to a clock signal, which has a clock cycle being dozens of nanoseconds (nsecs). The input/output buffer continuously transmits a predetermined volume of data according to the clock cycle or clock signal speed. However, a time for the sense amplifier to read data from flash memory cells is dozens of nsecs, and a time for the sense amplifier to write the data to the flash memory cells is hundreds of nsecs-dozens of microseconds (&mgr;secs). Thus, both the data reading and the data writing speed are slower than the data processing speed of the input/output pins. Accordingly, a data buffer is required to buffer differences of volume of data and of data transmission speed during the data reading and the data writing processes.
A capacity of the data buffer should be equal to a minimum volume of data that the data pins continuously receive. Generally, the minimum volume of received data is equal to data in a row of a memory. An access time of the data buffer should be faster than a data transmission time of the input/output buffer. The data buffer serves as an embedded memory provided in the programmable memory and mainly employs a latch array or a CMOS SRAM array, etc. therefor.
FIG. 1
is a circuit diagram of a related art data buffer for a multi-state programmable memory. As shown in
FIG. 1
, the related art data buffer for the multi-state programmable memory is provided with a cell array
1
having a plurality of columns, a plurality of sense amplifiers
2
that are respectively connected to a corresponding one of the columns of the cell array
1
and a plurality of data registers
3
each having a couple of inverters, for example INV
3
-
1
A, INV
3
-
1
B. The inverters INV
3
-
1
A and INV
3
-
1
B have inputs and outputs respectively connected to each other to latch a corresponding one of the sense amplifiers
2
. An input/output buffer
4
is connected to each output of the data registers
3
.
As described above, the related art data buffer has various disadvantages. When the construction of the sense amplifiers is simple, each column of the programmable memory can be connected to a corresponding one of the sense amplifiers
2
. Thus, each of the sense amplifiers
2
is connected to a latch, which is a corresponding one of the data registers
3
, to serve as the data buffer. However, if the size of each of the sense amplifiers is so large that each column can not be connected to the sense amplifiers, it is very difficult or impossible to array the latches. Also, the data buffer for the multi-state programmable memory should process data of at least 2 bits from the sense amplifiers. However, the related art data register has a problem processing the two or more bit data in a multi-state programmable memory.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data buffer and method that substantially obviates one or more problems are caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a data buffer that effectively processes data in a multi-state programmable memory regardless of volume and processing speed of the data and a method for using same.
Another object of the present invention is to provide a data buffer and method for a multi-state programmable memory that selectively couples data in a multi-state memory cell to input/output terminals.
To achieve at least these objects and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a data buffer for a multi-state programmable memory includes a sense amplifier formed in a plurality of columns for temporarily storing data, a data register array configured as the number of input/output buffer pins, each array has rows corresponding to the number of cells to be processed by each sense amplifier, a plurality of upper read/write circuits connected between the data register array and the input/output buffers, a plurality of lower read/write circuits connected between the data register array and the sense amplifiers, an upper and a lower switch circuits for connecting the data register array to the upper read/write circuits and to the lower read/write circuits, respectively, and a decoder-having a plurality of outputs to select a plurality of wordlines of the data register array.
To further achieve the above objects in a whole or in parts, a method for accessing in a page mode data of a multi-state programmable memory having a matrix of memory cells, data of the memory cells being accessed using a buffer and a sense amplifier via a data register array storing a plurality of data pages, according to the present invention is provided that includes receiving data in a first page of the data register array from at least one of the buffer and the sense amplifier in a page mode and concurrently transmitting data from a second page of the data register array to at least one of the input/output buffer and the sense amplifier in the page mode.
To further achieve the above objects in a whole or in parts, a method for accessing a multi-state programmable memory using a data buffer according to the present invention is provided that includes writing data to a first page of a first data register array selected by a first switch circuit using a first read/write circuit at a sense amplifier clock speed, transmitting the data from the first page to a buffer selected by a second switch circuit using a second read/write circuit at a buffer clock speed and concurrently writing data to a second page of the register array selected by the first switch circuit using the first read/write circuit at the sense amplifier clock speed and transmitting the data from the second page selected by the second switch circuit to the buffer at the buffer clock speed.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 4463443 (1984-07-01), Frankel et al.
patent: 5042013 (1991-08-01), Sato
patent: 5130704 (1992-07-01), Ogawa et al.
patent: 5170157 (1992-12-01), Ishii
patent: 5297029 (1994-03-01), Nakai et al.
patent: 5559736 (1996-09-01), Matsukawa et al.
patent: 6101135 (2000-08-01), Lee

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