Data buffer-controlled digital clock regenerator

Details Data buffer-controlled digital clock regenerator Data buffer-controlled digital clock regenerator

2007-05-01

2007-05-01

Tran, Khanh (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C370S517000, C327S152000

Reexamination Certificate

active

10620145

ABSTRACT:
A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.

REFERENCES:
patent: 5220581 (1993-06-01), Ferraiolo et al.
patent: 5245637 (1993-09-01), Gersbach et al.
patent: 5796796 (1998-08-01), Wang
patent: 6092128 (2000-07-01), Maas et al.
patent: 6810098 (2004-10-01), Paul et al.
patent: 6917660 (2005-07-01), Song
patent: 7100066 (2006-08-01), Jeong
Lärs Erup, Floyd M. Gardner, And Robert A. Harris. Interpolation in digital modems—Part II: Implementation and performance. IEEE Transactions on Communication, 41 (6) :998-1008, Jun. 1993.
Timo I. Laasko, Vesa Valimaki, Matti Karjalainen, and Unto K. Laine. Splitting the unit delay. IEEE Signal Processing Magazine, pp. 30-60, Jan. 1996.
Heinrich Meyer, Marc Moeneclaey, and Stefan A. Fechtel. Digital Communication Receivers: synchronization, channel estimation and signal processing. John Wiley & Sons, 1998.

Affiliated with

Also associated with

Rating

Data buffer-controlled digital clock regenerator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data buffer-controlled digital clock regenerator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data buffer-controlled digital clock regenerator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3766122