Data buffer circuit, interface circuit and control method...

Details Data buffer circuit, interface circuit and control method... Data buffer circuit, interface circuit and control method...

2005-04-11

2008-11-18

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

C326S093000, C326S094000, C326S095000, C326S096000, C326S097000, C326S098000, C710S052000, C710S058000, C711S167000, C711S217000, C711S218000, C711S219000, C713S400000, C713S401000

Reexamination Certificate

active

07454589

ABSTRACT:
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

REFERENCES:
patent: 5978891 (1999-11-01), Takeda
patent: 2002/0023238 (2002-02-01), Yamada et al.
patent: 05-073510 (1993-03-01), None
patent: 05-224920 (1993-09-01), None
patent: 8-511384 (1996-11-01), None
patent: 2000-305895 (2000-11-01), None
patent: 2001-319227 (2001-11-01), None

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