Electrical computers and digital processing systems: memory – Address formation
Reexamination Certificate
1998-02-18
2001-10-30
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
C711S210000, C711S211000, C711S212000, C711S214000, C711S215000
Reexamination Certificate
active
06311258
ABSTRACT:
Microfiche Appendix: There are 2 microfiche in total, and 103 frames in total.
FIELD OF THE INVENTION
The present invention relates to the data store apparatus and method for storing data objects in an image processing system, and in particular an apparatus that is reconfigurable to multiple arrangements and has particular application in a hardware accelerator used in an image processing system.
BACKGROUND OF THE INVENTION
In an image processing system, complex algorithms are often implemented in a hardware image processor to accelerate image production. Data buffers are sometimes used to improve the performance of such processors. Unfortunately it is expensive to have a number of data buffers each dedicated to a particular image operation. Hence there is a general need to minimize the amount of data buffers required to be utilized in an image processor architecture, especially one that carries out many different types of operations.
SUMMARY OF THE INVENTION
It is an object of the present invention to ameliorate one or more disadvantages of the prior art.
According to one aspect of the invention there is provided a data store apparatus comprising: encoding means for receiving incoming data objects, and for encoding the incoming data objects using an encoding scheme which is dependent upon one of a multiplicity of operating modes of the data store apparatus; storage means for storing the encoded incoming data objects in accordance with said operating mode; decoding means for decoding the output of the storage means in accordance with said operating mode; address generation means for generating the read and write addresses to memory modules comprising the storage means in accordance with said operating mode; and control means for generating control signals for controlling the storage of the data objects in the storage means.
According to another aspect of the invention there is provided a data store apparatus for storing first data objects containing a plurality of first data items and for storing second data objects containing one or more second data items, said apparatus comprising: first rearrangement means for rearranging the order of the first data items within the first data objects in accordance with a first rearranging mode and for outputting said rearranged first data objects; storage means consisting of a plurality of separately addressable memory banks, said storage means organised as a plurality of memory lines, each memory line including a memory location from each memory bank; write means for writing said first rearranged data objects in said plurality of storage means in accordance with a first write mode whereby said first data objects are stored in separate said memory lines and for writing said second data objects in said plurality of storage means in accordance with a second write mode, read means for simultaneously and separately reading a plurality of said first data items, each from a different one of said first data objects, from said plurality of memory banks in accordance with a first read mode and for reading one or more said second data objects from said plurality of storage means in accordance with a second read mode; second rearrangement means for rearranging the order of said plurality of read first data items in accordance with a second arranging mode; and control means for generating control signals for controlling the rearranging modes, the write modes and the first read modes.
According to another aspect of the invention there is provided a method for storing first data objects containing a plurality of first data items and for storing second data objects containing one or more second data items in storage means consisting of a plurality of separately addressable memory banks, said storage means organised as a plurality of memory lines and each memory line including a memory location from each memory bank, said method comprising the steps of: rearranging the order of the first data items within the first data objects in accordance with a first rearranging mode and for outputting said rearranged first data objects ; writing said first rearranged data objects in said plurality of storage means in accordance with a first write mode whereby said first data objects are stored in separate said memory lines and writing said second data objects in said plurality of storage means in accordance with a second write mode, simultaneously and separately reading a plurality of said first data items, each from a different one of said first data objects, from said plurality of memory banks in accordance with a first read mode and reading one or more said second data objects from said plurality of storage means in accordance with a second read mode; rearranging the order of said plurality of read first data items in accordance with a second arranging mode; and generating control signals for controlling the rearranging modes, the write modes, and the read modes.
In the following detailed description, the reader's attention is directed, in particular, to
FIGS. 111
to
126
and their associated description without intending to detract from the disclosure of the remainder of the description.
TABLE OF CONTENTS
1.0 Brief Description of the Drawings
2.0 List of Tables
3.0 Description of the Preferred and Other Embodiments
3.1 General Arrangement of Plural Stream Architecture
3.2 Host/Co-processor Queuing
3.3 Register Description of Co-processor
3.4 Format of Plural Streams
3.5 Determine Current Active Stream
3.6 Fetch Instruction of Current Active Stream
3.7 Decode and Execute Instruction
3.8 Update Registers of Instruction Controller
3.9 Semantics of the Register Access Semaphore
3.10 Instruction Controller
3.11 Description of a Modules Local Register File
3.12 Register Read/Write Handling
3.13 Memory Area Read/Write Handling
3.14 CBus Structure
3.15 Co-processor Data Types and Data Manipulation
3.16 Data Normalization Circuit
3.17 Image Processing Operations of Accelator Card
3.17.1 Compositing
3.17.2 Color Space Conversion Instructions
a. Single Output General Color Space (SOGCS) Conversion Mode
b. Multiple Output General Color Space Mode
3.17.3 JPEG Coding/Decoding
a. Encoding
b. Decoding
3.17.4 Table Indexing
3.17.5 Data Coding Instructions
3.17.6 A Fast DCT Apparatus
3.17.7 Huffman Decoder
3.17.8 Image Transformation Instructions
3.17.9 Convolution Instructions
3.17.10 Matrix Multiplication
3.17.11 Halftoning
3.17.12 Hierarchial Image Format Decompression
3.17.13 Memory Copy Instructions
a. General purpose data movement instructions
b. Local DMA instructions
3.17.14 Flow Control Instructions
3.18 Modules of the Accelerator Card
3.18.1 Pixel Organizer
3.18.2 MUV Buffer
3.18.3 Result Organizer
3.18.4 Operand Organizers B and C
3.18.5 Main Data Path Unit
3.18.6 Data Cache Controller and Cache
a. Normal Cache Mode
b. The Single Output General Color Space Conversion Mode
c. Multiple Output General Color Space Conversion Mode
d. JPEG Encoding Mode
e. Slow JPEG Decoding Mode
f. Matrix Multiplication Mode
g. Disabled Mode
h. Invalidate Mode
3.18.7 Input Interface Switch
3.18.8 Local Memory Controller
3.18.9 Miscellaneous Module
3.18.10 External Interface Controller
3.18.11 Peripheral Interface Controller
APPENDIX A—Microprogramming
APPENDIX B—Register tables
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Chung Wing Yan
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Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Nguyen Than
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