Data-bit redundancy in semiconductor memories

Details Data-bit redundancy in semiconductor memories Data-bit redundancy in semiconductor memories

1997-12-30

1999-03-02

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523106, G11C 700

Patent

active

058779922

ABSTRACT:
This invention provides a data bit redundancy method and apparatus that permits the replacement of faulty bitlines on a data bit basis as opposed to a column address basis. This invention provides a semiconductor memory device having memory cells arranged in columns and rows. Normal local data lines are connected to a global data line via a first switch. A redundant memory data line is connected to the global data line via a second switch. A control generating first and second control signals are coupled to the respective first and second switches for operating the switch in response to a status of a fuse component, whereby when the fuse is intact the normal data lines are connected to the global data line and when the fuse is blown the redundant data lines are connected to the global data line, thus not requiring additional redundancy address decoding circuitry.

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