Data processing: measuring – calibrating – or testing – Measurement system – Temperature measuring system
Reexamination Certificate
2002-04-24
2004-09-14
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Temperature measuring system
C702S099000
Reexamination Certificate
active
06792379
ABSTRACT:
BACKGROUND OF INVENTION
This invention relates the use of data obtained by testing integrated circuit (IC) chips to control the performance of the IC chip. In particular, it relates to simulating the operation of an integrated circuit chip and programming the reference data table of the chip with information based on data obtained from that simulation.
Integrated circuit chips are made by depositing and removing insulating and conducting layers on silicon wafers using processes such as photolithography, oxidation, and chemical vapor deposition. During these processes, the chips are subjected to high temperatures and exposure to various gases and plasmas. It is nearly impossible to hold the conditions exactly the same for every chip on a wafer. As a result, the chips differ in the thicknesses of their different layers and in the diffusion profiles of dopants such as boron or phosphorus. These physical differences mean that the chips have different optimal operating parameters.
Each wafer can have many chips on it and each chip may comprise thousands or even millions of transistors. Each transistor has a characteristic threshold voltage, i.e., the source-to-gate voltage that must be exceeded to turn the transistor ON. However, even when the transistor is OFF, a small amount of current, the subthreshold leakage current, leaks between the drain and the source. Since each IC chip comprises a large number of transistors, the tiny subthreshold leakage current for each transistor adds up to a substantial current for the entire chip. This current loss is especially important for computers that run on batteries, such as lap-tops.
The subthreshold leakage current can be reduced by increasing the threshold voltage. One way to increase the threshold voltage of a chip is by increasing the back-bias voltage, the voltage applied to the substrate of the transistor. However, a higher threshold voltage increases the time required for the current to charge up the logical threshold voltage, which increases the switching time of the transistor and lowers the clock speed of the chip. Thus, low power consumption and high clock speed are contradictory requirements. Nevertheless, IC chips for use in mobile computers are now required to have both higher program execution speed and lower power consumptions. In order to attain those contradictory performance characteristics, the range of permitted threshold voltages and other characteristics has become narrower and narrower. In some cases, at least two different threshold voltages or other control conditions are used. In U.S. Pat. No. 5,710,800, for example, the supply voltage and clock rate is controlled using an internal control circuit.
In U.S. Pat. No. 6,345,362, each functional unit in an IC chip has an independently controllable threshold voltage. The instructions to a chip are decoded to determine which functional units are needed to execute the instructions. The process speed of the units can then be adjusted to the optimal power level. A status table indicates the present power status of each of the functional units and a requirements table identifies the units required to execute a particular instruction.
In U.S. Pat. No. 5,996,083, the rate of program execution is controlled by software that changes the data bus width and the power latency values. The power consumption per second can be decreased by changing the data bus width from 64 bits to 32 bits, but this approximately doubles the program execution time. The execution time for each program is determined by the clock rate and the power latency, which is the time required to change the applied voltage or the status condition (e.g., standby or execute). The power latency time is needed to stabilize the applied power and the program execution and it adds to the total consumption of power and the total operation speed. Changes in data bus width and power latency controlled by the instruction program. In U.S. Pat. No. 5,996,083, the power consumption or program execution speed is improved by changing the program using an internal control circuit. But the values the control circuit works with are the values designed for the chip.
SUMMARY OF INVENTION
In this invention, the values entered into in a reference data table on an IC chip are based on actual measurements made on that chip. That is, before a chip shipped, it is tested, both after the wafer is made and after individual chips have been cut from the wafer and assembled. During those tests, the optimal values for various parameters for that chip can be determined. These experimentally-determined values are entered in the reference data table. In this way, each chip can be individually optimized according to its own properties.
The method of this invention may also result in fewer rejected chips. That is, a chip that is designed to operate at, for example, 120 MHz at 3.3 volts, but cannot do so is rejected. But that chip may be able to operate at 120 MHz at 3.5 volts. According to the method of this invention, the 3.5 volt value would be used and the chip would not be rejected.
The method of this invention can be used to reduce the power consumed by a chip, maximize its operating speed, reduce its operating voltage, or achieve a balance of high speed and low power consumption.
REFERENCES:
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patent: 5781060 (1998-07-01), Sugawara
patent: 5996083 (1999-11-01), Gupta et al.
patent: 6006169 (1999-12-01), Sandhu et al.
patent: 6320453 (2001-11-01), Manning
patent: 6345362 (2002-02-01), Bertin et al.
patent: 6574577 (2003-06-01), Stapleton et al.
patent: 6675360 (2004-01-01), Cantone et al.
patent: 2004/0004570 (2004-01-01), Lehmann
Fuerle Richard D.
Hoff Marc S.
Miller Craig Steven
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