Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1994-11-22
1996-01-09
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
3701001, 375346, 375354, H03K 513
Patent
active
054831806
ABSTRACT:
Disclosed is a data and clock recovery circuit possible to restore data signals and synchronizing clocks which have been distorted during transmission over the communication line, which is comprised of the following: main oscillation loop that maintains operating frequency by using the input data and a self oscillation loop that operates using reference clock embedded within multiplex communication devices when communication lines get shorted or when power is restored after an outage; loop selecting switch which selects the main oscillation loop during normal operating mode and selects the self oscillation loop when communication line shorts or when the power is being restored; data signal monitor which connects to the loop selecting switch and determines communication line shorting by monitoring data transmission; power supply monitor which connects to the loop selecting switch and monitors the restoration of power after an outage. The circuit maintains stable operation and supplies stable output to multiplex communication devices not only during the normal operating conditions, but also when there is a communication line shorting or restoration of power after a power supply outage.
REFERENCES:
patent: 4232197 (1980-11-01), Acampora et al.
patent: 4675861 (1987-06-01), Uttermark
patent: 4754225 (1988-06-01), Minuhin
patent: 5103466 (1992-04-01), Bazes
patent: 5327466 (1994-07-01), Marinaro
patent: 5406561 (1995-04-01), Arai
patent: 5418822 (1995-05-01), Schlachter et al.
Chai Sang-Hoon
Choi Hae-Wook
Kwak Myung-Shin
Park Mun-Yang
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