Data amplifier having reduced data lines and/or higher data...

Details Data amplifier having reduced data lines and/or higher data... Data amplifier having reduced data lines and/or higher data...

2005-09-27

2005-09-27

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S300000, C711S100000, C712S033000, C365S063000

Reexamination Certificate

active

06950898

ABSTRACT:
A data amplifier configured to allow for fewer data lines and/or increased processing speeds. Specifically, multiple helper flip-flops are used to prefetch data in a data amplifier. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines. Alternatively, the number of data lines can be maintained and faster bus processing speeds may be realized.

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“A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory” by Yamauchi, T.; Morooka, Y.; Ozaki, H. (abstract only) Publication date: Jun. 8-10, 1995.

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