Data alignment micro-architecture systems and methods

Details Data alignment micro-architecture systems and methods Data alignment micro-architecture systems and methods

2004-05-03

2008-08-12

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

C712S204000

Reexamination Certificate

active

07412584

ABSTRACT:
Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an indication to the shifter of an amount by which the data is to be shifted. In one embodiment, the control logic provides support for speculative execution. The control logic may also permit multiplexing of big endian and little endian data alignment operations, and/or multiplexing of data alignment operations with non-data alignment operations. In one embodiment, the memory unit, shifter, and control logic are integrated within a processing unit, such as a microengine in a network processor.

REFERENCES:
patent: 5423010 (1995-06-01), Mizukami
patent: 5450557 (1995-09-01), Kopp et al.
patent: 6061779 (2000-05-01), Garde
patent: 6330631 (2001-12-01), Crosland
patent: 2003/0167390 (2003-09-01), Gorman et al.

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