Data alignment between buses

Details Data alignment between buses Data alignment between buses

1999-02-03

2001-12-11

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S022000, C710S023000, C710S027000, C710S033000, C710S065000, C710S120000, C708S209000, C708S233000, C708S501000, C708S603000, C708S625000, C712S028000, C712S029000

Reexamination Certificate

active

06330631

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention to transferring data between buses in a computer system. In particular, the invention relates to a bus bridge for transferring data between buses, to a DMA controller for transferring data between buses, to a computer system incorporating such a bus bridge and/or DMA controller and to a method of transferring data between buses.
In the present context, a bridge is a mechanism for transferring data between buses. It is commonplace in modem computer systems for multiple buses to be provided, and for a bridge mechanism to be provided for transferring data between the buses. The bridge mechanism may take many different forms and may incorporate other functions. For example, it is known to provide a DMA controller between an I/O bus and another bus forming part of the computer system.
For different buses, it may be desirable to have different byte address alignments. The present invention addresses the problem of providing efficient transfer between buses with selectable bus alignment on the respective buses.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with one aspect of the invention, there is provided a bus bridge for a computer system. The computer system can includes a first bus and a second bus with the bridge being locatable between the first and second buses. The bridge includes a shifter having an input connected to receive bytes from one of the first and second buses and an output providing a selectable shift to the received bytes. It also includes an accumulator having an input connected to receive the output of the shifter and providing selective accumulation of the shifted bytes, the accumulator having an output for supplying realigned bytes to be passed to the other of the first and second buses.
The combination of the shifter and the accumulator permits a desired amount of shift to be combined with the accumulation of selected bytes, or bits, to realign sets of bytes from one bus and to form sets of bytes for the other bus. This structure enables flexible transfer of bytes with an arbitrary realignment in an efficient manner. Burst transfer is also possible by operating the shifter and the accumulator unit in successive cycles for successive sets of input bytes input from the input bus.
Control logic provides control signals to select the shift applied to the received bytes and to select the bytes, or bits, to be accumulated from the shifted bytes. The shifter and the accumulator are operable in successive phases within a cycle. In one cycle, a first set of bytes, or bits, from the shifted bytes may be selected for one set of output bytes. In another cycle, a second set of bytes, or bits, may be selected from the shifted bytes for another set of output bytes.
The control logic is arranged to determine the control signals for successive cycles and phases to effect a burst transfer of bytes from one bus to the other bus.
The accumulator can include an output register. In the first phase, accumulation of an output set of realigned bytes may be completed by registering selected parts of a shifted input set of bytes at corresponding parts in the output register. In, the second phase, accumulation of a subsequent output set of realigned bytes may be started by registering remaining parts of a shifted input set of bytes at corresponding parts in the output register.
It should be noted that a set of bytes may form a word, or may form part of a word, depending on the relative bus widths and the width of the shift and accumulate unit.
In an embodiment of the invention, the bridge further comprises a buffer for buffering sets of bytes, the buffer being connectable between the first bus and the shifter. The buffer can be connected between the first bus and the shifter when bytes are to be transferred from the first bus to the second bus, or between the accumulator and the first bus when bytes are to be transferred from the second bus to the first bus. This provides for flexible buffering of data to take account of possible different speeds of operation of the timings for the first and second buses.
In order to provide the selected ordering of the buffer unit and the shift and accumulate unit as described above, the buffer and the shifter are preferably associated with input multiplexors.
The input multiplexor of the buffer unit can include a first input connectable to receive bytes from the first bus, a second input connected to receive bytes from the accumulator and an output connected to output bytes to a buffer of the buffer unit.
The input multiplexor of the shifter can comprise a first input connected to receive bytes from the second bus, a second input connected to receive bytes from an output of the buffer unit and an output connected to output bytes to the shifter.
An embodiment of the bus bridge forms a direct memory access controller, for example for connection between an I/O bus and another processor bus, for example a bus operable under an appropriate system bus (SBus) protocol.
According to another aspect of the invention, therefore, there is provided a direct memory access controller for a computer system having a first bus and a second bus. The direct memory access controller is locatable between the first and second buses. It comprises a shifter having an input connected to receive bytes from one of the first and second buses and an output providing a selectable shift to the received bytes. It also comprises an accumulator having an input connected to receive the output of the shifter and providing selective accumulation of the shifted bytes, the accumulator having an output for supplying realigned bytes to be passed to the other of the first and second buses.
In accordance with a further aspect of the invention, there is provided a computer system having a first bus, a second bus and a bus bridge as set out above between the first and second buses.
In accordance with yet a further aspect of the invention, there is provided a method of transferring data between a first bus and a second bus in a computer system. The method comprises steps of:
shifting bytes received from one of the first and second buses to providing a selectable shift to the received bytes; and
performing selective accumulation of the shifted bytes for supplying realigned bytes to be passed to the other of the first and second buses.
The steps are repeated in successive cycles, with a set of bytes being received in each cycle. The set of bytes can be a word, or part of a word as described above.
In a first phase of a cycle, accumulation of an output set of realigned bytes can be completed by registering bytes, or bits, from selected positions of a shifted input set of bytes at corresponding positions in an output register; and
in a second phase of a cycle, accumulation of a subsequent output set of realigned bytes can be started by registering bytes, or bits, from remaining positions of a shifted input set of bytes at corresponding positions in the output register
For transfers from the first bus to the second bus, bytes are buffered prior to being processed by the shifter and the accumulator, and, for transfers from the second bus to the first bus, bytes are buffered after being processed by the shifter and the accumulator.
For transferring a burst of bytes between the first and second buses, the method can include one or more of the following steps:
in an initial stage, selected bits of shifted bytes from up to two cycles are accumulated to form an initial set of output bytes;
in an intermediate stage, selected bits of shifted bytes from two cycles are accumulated to form intermediate sets of output bytes; and
in a final stage, selected bits of shifted bytes from up to two cycles are accumulated to form a final set of output bytes.
For transferring a burst of bytes between

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