Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-07-01
2008-07-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07395517
ABSTRACT:
A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
REFERENCES:
patent: 4879731 (1989-11-01), Brush
patent: 5701517 (1997-12-01), Carpenter
patent: 5860094 (1999-01-01), Junya
patent: 5973628 (1999-10-01), McDonnell
patent: 6003122 (1999-12-01), Yarch
patent: 6151682 (2000-11-01), van der Wal et al.
patent: 6175911 (2001-01-01), Oberman
patent: 6539467 (2003-03-01), Anderson
patent: 6829697 (2004-12-01), Davis et al.
patent: 6870831 (2005-03-01), Hughes et al.
patent: 7130984 (2006-10-01), Chard et al.
L. B. Arimilli, et. al., Data Alignment Logic Comprising Mux to Mux Stages, IBM Technical Disclosure Bulletin, vol. 38, No. 7, Jul. 1995, pp. 501-504.
Aldebert Jean-Paul
Basso Claude
Calvignac Jean Louis
Verplanken Fabrice Jean
Cockburn Joscelyn G.
International Business Machines - Corporation
Siek Vuthe
Winstead P.C.
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