Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Reexamination Certificate
2007-02-06
2007-02-06
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Generating prefetch, look-ahead, jump, or predictive address
C711S217000, C711S218000, C710S022000
Reexamination Certificate
active
10432203
ABSTRACT:
A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.
REFERENCES:
patent: 4727474 (1988-02-01), Batcher
patent: 5155823 (1992-10-01), Tsue
patent: 5467459 (1995-11-01), Alexander et al.
patent: 5835788 (1998-11-01), Blumer et al.
patent: 6070003 (2000-05-01), Gove et al.
patent: 6131092 (2000-10-01), Masand
patent: 2001/0052062 (2001-12-01), Lipovski
patent: 2004/0064670 (2004-04-01), Lancaster et al.
Lea, ASP Modules: Cost-Effective Building-Blocks for Real-Time DSP System, Journal of VLSI Signal Processing, 1989, pp. 69-84, Kluwer Academic Publishers, Boston.
Lancaster John
Whitaker Martin
Aspex Technology Limited
Bragdon Reginald
Dinsmore & Shohl LLP
Flournoy Horace L.
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