Data address security device and method

Details Data address security device and method Data address security device and method

2007-07-17

2007-07-17

Starks, Jr., Wilbert L. (Department: 2129)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C708S250000, C375S224000

Reexamination Certificate

active

10902406

ABSTRACT:
Methods and devices for monitoring transactions on a bus are disclosed herein. An embodiment of the device comprises a memory component and a comparator component. The memory component stores at least one address. The comparator component is operatively connected to the memory component and the bus. The comparator component compares an address transmitted over the bus with the stored address for purposes of identifying impermissible addresses. The device causes a transaction associated with an impermissible address to be aborted.

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patent: 5963543 (1999-10-01), Rostoker et al.
patent: 6278729 (2001-08-01), Thompson
patent: 6282239 (2001-08-01), Thompson
patent: 6671758 (2003-12-01), Cam et al.
patent: 6751205 (2004-06-01), Menon et al.
patent: 7165084 (2007-01-01), Crispin et al.

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