Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-03-31
2001-07-03
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S157000
Reexamination Certificate
active
06256717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data access controller and data access control method, and particularly to a data access controller and data access control method which are intended for making access to the SRAM efficiently in the modulation/demodulation process, error detection/correction process, or data transfer process, for example.
2. Description of the Prior Art
In recording or playing back data to/from a recording medium such as a mini disc (MD) (trademark), it is necessary to prepare a static random access memory (SRAM) for each error correction code (ECC) block which is the unit of data recording and playback, and encode or decode an ECC block concurrently to the process of the modulator/demodulator (modem). On this account, it is a conceivable manner to have two or more SRAMS. In the following explanation, two SRAMs will be called a first SRAM and second SRAM.
At data recording, for example, data to be recorded is written into the first SRAM, the data is read out of the first SRAM by an ECC encoder, and the data, with C1 and C2 parities being appended thereto (will be termed “ECC block”), is written into the second SRAM. Concurrently with these operations, an ECC block is read out of the second SRAM by the modulator, and it is modulated and recorded on the MD.
At data playback, an ECC block is read out of the MD, and it is demodulated by the demodulator and written into the second SRAM. Concurrently to these operations, an ECC block is read out of the second SRAM, error detected and corrected by the ECC decoder, and written into the first SRAM.
Based on the provision of two SRAMs, it is possible to carry out concurrently the modulation/demodulation process by the modem and the encoding process by the ECC encoder or error detection/correction process by the ECC decoder.
However, the presence of two SRAMs results in an increased number of bus lines and a larger circuit scale. Moreover, the memory access time for external input/output is so tight that it is required for the external input/output operation to use another buffer SRAM, or reduce the number of times of performing the ECC detection/correction process, or raise the master clock frequency.
SUMMARY OF THE INVENTION
The present invention is intended to deal with the foregoing prior art situation, and its prime object is to provide a data access controller and data access control method capable of reducing the circuit scale inclusive of SRAMs used for the modulation/demodulation process and error detection/correction process, and enhancing the error correcting ability.
The inventive data access controller comprises means of holding data, means of generating addresses for accessing to the memory means in correspondence with multiple kinds of processes, and means of providing the addresses on a time-slice basis for the memory means, wherein the memory means is accessed for data reading and writing at addresses given on a time-slice basis by the address providing means, and the address generation means generates addresses such that reading-out of data from a certain memory address by a certain one of the multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by a certain other process.
The inventive data access controller comprises means of holding data, means of generating addresses for making access to the memory means in correspondence to multiple kinds of processes, means of providing the addresses on a time-slice basis for the memory means, means of generating a first clock signal, and means of generating a second clock signal which is different in phase from the first clock signal, wherein the address generation means and address providing means operate in accordance with the first and second clock signals, and the memory means is accessed for data input/output by being timed to the rising of the first and second clock signals.
The inventive data access controller comprises means of holding data, means of generating addresses for making access to the memory means in correspondence to multiple kinds of processes, means of providing the addresses on a time-slice basis for the memory means, and means of appending C1 and C2 parities to data, wherein the memory means writes and reads out data at addresses given on a time-slice basis by the address providing means, the parity appending means distributes the C2 parities so that their memory addresses scatter, and the address generation means generates different addresses for the case of the ECC encoding process in which the C1 and C2 parities are appended to data and for the case of the data modulation process or data demodulation process.
The inventive data access control method comprises the steps of generating addresses such that reading-out of data from a certain memory address by a certain one of multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by a certain other process, and providing the addresses on a time-slice basis for the memory means.
In the data access controller, the memory means holds data, the address generation means generates addresses for making access to the memory means in correspondence to multiple kinds of processes, and the address providing means provides the addresses on a time-slice basis for the memory means. The memory means is accessed for data reading and writing at addresses given on a time-slice basis by the address providing means, and the address generation means generates addresses such that reading-out of data from a certain memory address by a certain one of the multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by a certain other process.
In the data access controller, the memory means holds data, the address generation means generates addresses for making access to the memory means in correspondence to multiple kinds of processes, the address providing means provides the addresses on a time-slice basis for the memory means, the first clock signal generation means generates a first clock signal, and a second clock signal generation means generates a second clock signal which is different in phase from the first clock signal. The address generation means and address providing means operate in accordance with the first and second clock signals, and the memory means is accessed for data input/output by being timed to the rising of the first and second clock signals.
In the data access controller, the memory means holds data, the address generation means generates addresses for making access to the memory means in correspondence to multiple kinds of processes, the address providing means provides the addresses on a time-slice basis to the memory means, the parity appending means appends C1 and C2 parities to data. The memory means writes and reads out data at addresses given on a time-slice basis by the address providing means, the parity appending means distributes the C2 parities so that their memory addresses scatter, and the address generation means generates different addresses for an ECC encoding process in which the C1 and C2 parities are appended to data and for a data modulation process or data demodulation process.
In the data access control method, memory addresses are generated such that reading-out of data from a certain memory address by a certain one of multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by a certain other process, and the addresses are given on a time-slice basis to the memory means.
REFERENCES:
patent: 4742543 (1988-05-01), Frederiksen
patent: 5305319 (1994-04-01), Sowell
patent: 5884099 (1999-03-01), Klingelhofer
patent: 5917792 (1999-06-01), Shigenobu et al.
Inoue Koji
Shigenobu Masahiro
Todo Hirofumi
Ellis Kevin L.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Sony Corporation
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