Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-10-20
2000-07-11
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711157, G06F 1316
Patent
active
060887753
ABSTRACT:
A data access controller has an SRAM adapted to hold two ECC blocks so that the SRAM is used efficiently for multiple kinds of processes. At playback of data, writing of ECC block A from a demodulator and an ECC process for ECC block B begin simultaneously. When the ECC process ends, release of the ECC block B to the outside begins. When the writing of ECC block A ends, the ECC process for the ECC block A begins and, at the same time, writing of ECC block B from the demodulator begins.
REFERENCES:
patent: 4742543 (1988-05-01), Frederiksen
patent: 5305319 (1994-04-01), Sowell
patent: 5884099 (1999-03-01), Klingelhofer
patent: 5917792 (1999-06-01), Shigenobu et al.
Inoue Koji
Shigenobu Masahiro
Todo Hirofumi
Chan Eddie P.
Ellis Kevin L.
Sony Corporation
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