Data acceleration mechanism for a multiprocessor shared...

Details Data acceleration mechanism for a multiprocessor shared... Data acceleration mechanism for a multiprocessor shared...

2005-12-06

2005-12-06

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S143000, C711S152000

Reexamination Certificate

active

06973548

ABSTRACT:
A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.

REFERENCES:
patent: 5752264 (1998-05-01), Blake et al.
patent: 6092156 (2000-07-01), Schibinger et al.
patent: 6389515 (2002-05-01), Schibinger et al.
patent: 6738872 (2004-05-01), Van Huben et al.
patent: 6792507 (2004-09-01), Chiou et al.
patent: 2001/0013089 (2001-08-01), Wolf-Dietrich

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