Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-05
2004-09-28
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06799312
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to forming images in a layer of resist material with a variable shaped electron beam and more specifically to methods of improving critical dimension and XY critical dimension control.
(2) Description of the Related Art
Electron beam exposure systems using an electron beam with a variable shape are often used in direct exposure of a layer of resist material formed on a substrate such as an integrated circuit wafer or a mask substrate. However critical dimension control can be inadequate for the cutting of the dark line around the circumference of the pattern. Methods providing improved control of dark line critical dimension and XY critical dimension are important.
U.S. Pat. No. 5,578,821 to Meisberger et al. describes an electron beam inspection system and method. In the inspection configuration there is a comparison system for comparing the pattern on a substrate with a second pattern.
U.S. Pat. No. 4,698,509 to Wells et al. describes a pattern generator for supplying beam deflection and blanking signals in an electron beam lithography system.
U.S. Pat. No. 5,808,892 to Tu describes an electron beam processing method for improving micron and submicron line quality and resolution.
U.S. Pat. No. 5,888,682 to Nakasuji describes methods and apparatus for accurately performing proximity-effect correction.
SUMMARY OF THE INVENTION
Electron beam exposure systems are often used in direct exposure of a layer of resist material formed on a substrate such as an integrated circuit wafer or a mask substrate. Advantages in processing efficiency can be gained by using an electron beam having a variable shape. The variable shaped electron beam, however, has less critical dimension control and beam size stability than an electron beam using a fixed beam shape. This loss of critical dimension control can be a problem at the outer circumference of a pattern element.
It is a principle objective of this invention to provide a method of using an electron beam exposure system having an electron beam with a fixed shape and a variable shape to form patterns in a layer of resist on an integrated circuit wafer while maintaining adequate critical dimension control and beam stability.
It is another principle objective of this invention to provide a method of using an electron beam exposure system having an electron beam with a fixed shape and a variable shape to form patterns in a layer of resist on a mask substrate while maintaining adequate critical dimension control and beam stability.
These objectives are accomplished by first setting the electron beam to a fixed beam size and shape. The fixed beam used has a square shape with a width set to provide optimum XY critical dimension control. A frame pattern is then formed around the outer perimeter of the original pattern, hereinafter referred to as the first pattern. The width of the frame pattern is a first distance, wherein the first distance is the width of the fixed beam which provides optimum XY critical dimension control. The fixed beam is then used to expose the frame pattern in a layer of resist. A remainder pattern which is the frame pattern and the first pattern subtracted from the full exposure field is then exposed in the layer of resist using an electron beam having a variable size and shape. This method maintains the advantages of the variable shape electron beam for most of the pattern exposure while maintaining critical dimension control at the critical dimension region of the first pattern.
REFERENCES:
patent: 4698509 (1987-10-01), Wells et al.
patent: 5250812 (1993-10-01), Murai et al.
patent: 5283440 (1994-02-01), Sohda et al.
patent: 5526279 (1996-06-01), Dick
patent: 5578821 (1996-11-01), Meisberger et al.
patent: 5661307 (1997-08-01), Tanaka et al.
patent: 5767521 (1998-06-01), Takeno et al.
patent: 5808892 (1998-09-01), Tu
patent: 5888682 (1999-03-01), Nakasuji
patent: 6093932 (2000-07-01), Nakajima
patent: 6162567 (2000-12-01), Watanabe
Fukuda et al, “Analysis of Critical Dimension Control for Optical-, EB-, and X-Ray Lithography Below the 0.2 um Region,” IEEE, 1995, pp. 77-78.
Lin Shy-Jay
Tsai Fei-Gwo
Ackerman Stephen B.
Prescott Larry J.
Saile George O.
Siek Vuthe
Taiwan Semiconductor Manufacturing Company
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