Damascene tri-gate FinFET

Details Damascene tri-gate FinFET Damascene tri-gate FinFET

2006-05-09

2006-05-09

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S149000, C257S213000

Reexamination Certificate

active

07041542

ABSTRACT:
A method of forming a fin field effect transistor includes forming a fin and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a dummy gate over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the dummy gate to form a trench in the dielectric layer and forming a metal gate in the trench.

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Co-pending U.S. Appl. No. 10/320,536, filed Dec. 17, 2002 entitled: “FinFET Gate Formation Using Reverse Trim of Dummy Gate,” 14 page specification, 11 sheets of drawings.
Co-pending U.S. Appl. No. 10/459,589, filed Jun. 12, 2003 entitled: “FinFET Gate Formation Using Reverse Trim and Oxide Polish,” 17 page specification, 28 sheets of drawings.
Co-pending U.S. Appl. No. 10/310,777, filed Dec. 6, 2002 entitled: “Damascene Gate Process with Sacrificial Oxide in Semiconductor Devices,” 19 page specification, 10sheets of drawings.
Co-pending U.S. Appl. No. 10/645,577, filed Aug. 22, 2003 entitled: “Sacrificial Oxide Protection During Dummy Gate Removal in Damascene Gate Process in Semiconductor Devices,” 19 page specification, 9sheets of drawings.
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Co-pending U.S. Appl. No. 10/720,166, filed Nov. 25, 2003 entitled: “Damascene Gate Process with Sacrificial Oxide in Semiconductor”; 19 page specification, 10 sheets of drawings.
Co-pending U.S. Appl. No. 10/838,228, filed May 5, 2004 entitled: “Sacrificial Oxide for Minimizing Box Undercut in Damascene FinFet”; 15 page specification, 12 sheets of drawings.

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