Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
2000-07-20
2001-08-07
Mills, Gregory (Department: 1763)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C438S725000, C438S579000, C438S637000, C438S638000, C438S585000, C438S723000, C438S734000, C438S750000
Reexamination Certificate
active
06270929
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a method for forming a gate structure with a contact area wider than a base area.
BACKGROUND OF THE INVENTION
Historically, gate structures having a base area with a width that is smaller than the gate contact area (e.g. T-gate and Y-gate structures) have been advantageous in several technologies. For example, MESFET, HEMT (variant of gallium arsenide field effect transistor technology) mainly used in satellite broadcasting receivers, high speed logic circuits and power modules have employed gate structures with bases smaller than the contact area. These types of devices are required in field effect transistors for operation in ultra-high frequency ranges. The advantage of employing a gate structure with a shorter gate length is that the channel of the gate is reduced resulting in an increased in speed and a decrease in power consumption. Reducing the distance over which the gate's field effect control of the electrons in the channel reduces the parasitic resistances and capacitances that limit device speed. A shorter gate length decreases the transmit time for carriers in the channel but also increases the series resistance of the gate electrode itself, slowing down the device and degrading the frequency characteristics of the device. Providing a gate structure with a smaller base than its contact area decreases the gate channel while providing a low gate series resistance due to the wider contact area and, thus, improving the devices drive current capability and performance.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as comers and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Recent advances in CMOS transistor architecture make use of the T-gate or Y-gate structures where the polysilicon gate electrode is narrowed in the gate regions and wider on top of the gate. This is due to the ever increasing demand for scaling down semiconductor devices and scaling down power consumption requirements. However, the current methods for forming a gate structure with a contact region wider than its base suffers from shortcomings. For example, the etch process which narrows the base of the structure are known to be difficult to control especially with local pattern density. This can lead to variation in the gate width and asymmetric implant profiles. Another problem is related to manufacturing controls. The “re-entrant” or overhung profile prevents direct measurement of the critical gate length.
In view of the above, there is an unmet need for improvements in methodologies for formation of gate structures with contact areas that are wider than the base area.
SUMMARY OF THE INVENTION
The present invention employs a damascene or inlaid process for forming a T-shaped gate electrode. A gate dielectric is grown over a silicon material. A very thin deposition of gate electrode material such as polysilicon is deposited over the gate dielectric material. A damascene “stencil” material or insulating material, such as an oxide, is then deposited to a thickness required for the final gate electrode thickness. A lithographic pattern is used to define a first opening in a “stencil film such as SiO
2
. The width of the lithographically defined structure is greater that the final gate length. The depth of the opening is less than the full oxide film thickness and can be controlled by a timed etch process. The next process step is to shrink the width of the lithographic pattern to the extent needed to achieve a final gate length. Methods for swelling resist are employed. A second etch completes the removal of the stencil in the gate region and defines the base of the T-gate and the resist material is then stripped. Standard SEM metrology can monitor the critical gate length. A standard polysilicon deposition and polish can be employed after removal of the resist. The stencil or oxide material is then removed and the exposed portion of the original thin polysilicon layer completes the formation of the desired T-gate structure.
One aspect of the invention relates to a method for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. A photoresist layer is formed over the insulating layer. An opening is the formed extending through the photoresist layer and partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. The photoresist layer is swelled to reduce the size of the opening in the photoresist layer. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The opening is then filled with a conductive material.
Another aspect of the present invention relates to another method for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. A photoresist layer is formed over the insulating layer. The photoresist layer is etched to form an opening in the photoresist layer exposing a portion of the underlying insulating layer. Another etching is performed on the exposed insulating layer to extend the opening partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. The photoresist layer is swelled to reduce the size of the opening in the photoresist layer. Yet another etch step is performed to extend the opening in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The opening is then filled with a conductive material. The insulating layer and the gate oxide and polysilicon layer underlying the conductive material are then removed.
Yet another aspect of the present invention provides for yet another method for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. A photoresist layer is formed over the insulating layer. The thick photoresist layer has a th
Lyons Christopher F.
Plat Marina
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Goudreau George
Mills Gregory
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