Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-05-18
2004-01-20
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S758000, C257S532000
Reexamination Certificate
active
06680542
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor device having a damascene structure incorporated therein and, more specifically, to a semiconductor device having a damascene structure incorporated therein and a metal-oxide-metal capacitor associated with the damascene structure and a method of manufacture therefor.
BACKGROUND OF THE INVENTION
As is well known, various active devices and structures are commonly formed within an integrated circuit. These various active devices and structures are what allow fast, reliable and inexpensive integrated circuits to be manufactured for today's ever competitive computer and telecommunication markets.
Interconnects, have gained wide acceptance and use in today's integrated circuit technology. As is well known, the semiconductor industry is currently moving toward low dielectric constant (low-k) materials and copper metal to form such interconnects. This is a result of the semiconductor industries' desire to reduce resistive capacitance delays associated with the higher dielectric constant materials, and take advantage of the benefits of using copper as the interconnect metal.
However, certain problems are encountered when forming traditional copper interconnects. The main problem stems from the difficulty of etching the copper metal to create the interconnect. In response, the industry adopted damascene strategies for fabricating these interconnects. To fabricate such damascene interconnects, the damascene interconnect structure would first be etched into the low-k material, followed by filling the structure with metal, typically copper. A benefit of the damascene technique is that it has fewer manufacturing steps per completed metal layer. Considering that devices of the near future will require as many as seven inter-level connections, such as vias, and a corresponding number of intra-level connections, such as wires or lines, damascene processing should lead to considerable cost and performance gains over traditional interconnect processing. Additionally, damascene strategies where both the via and wire are patterned, simultaneously etched, and simultaneously filled with metal, further reduces the number of processing steps.
Metal-oxide-metal (MOM) capacitors have also gained wide acceptance and use in today's integrated circuit technology. One who is skilled in the art is readily aware that a MOM capacitor comprises two conductive plates or electrodes separated by a dielectric surface film. Conventional processes to form a MOM capacitor traditionally include depositing a first metal layer, depositing an oxide layer followed by an oxide CMP, then depositing a second metal layer. In those areas where the MOM capacitor is not required, a subtractive metal etch is often performed to define the area in which the MOM capacitor is to be located. Unfortunately, however, given present day techniques, the incorporation of a MOM capacitor into an integrated circuit that has a damascene interconnect system is extremely difficult. This is due to the difficulty of etching copper that is used to form the interconnects and the electrodes of the MOM capacitor.
Accordingly, what is needed in the art is a device that incorporates a MOM capacitor into an integrated circuit having damascene interconnects, while avoiding the problems associated with the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating it on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.
Thus, in one aspect, the present invention provides a device and method wherein a MOM capacitor is formed within a damascene interconnect structure. Because the MOM capacitor is formed within a damascene interconnect structure, the etching steps typically associated with conventional processes are avoided. Moreover, fewer processing steps are required, thereby saving production costs and time.
The MOM capacitor, may in another embodiment, include a first capacitor electrode, a capacitor dielectric and a second capacitor electrode. In yet another embodiment, the first capacitor electrode of the MOM capacitor may be a second interconnect structure, the capacitor dielectric may be the dielectric etch stop layer and the second capacitor electrode may be a metal that comprises the damascene interconnect structure. In other embodiments, the dielectric etch stop layer may comprise silicon nitride, the interlevel dielectric layer may comprise silicon dioxide and the metal that comprises the damascene interconnect structure may comprise copper. Moreover, in an alternative embodiment, the first and second electrodes of the MOM capacitor damascene structure are preferably comprised of copper.
In another aspect of the invention, a barrier layer may be formed within the MOM capacitor damascene structure. The barrier layer may in another aspect, be tantalum nitride, tantalum or titanium nitride. However, one having skill in the art knows that other compatible barrier layers may be used.
In a preferred embodiment, the damascene interconnect structure and the MOM capacitor damascene structure are formed with a single mask. In an alternative embodiment a damascene structure opening and a MOM capacitor damascene opening are formed down to the dielectric etch stop layer. However, in a different embodiment, the MOM capacitor damascene interconnect structure opening is filled with a photoresist while the dielectric etch stop layers in the damascene interconnect structure opening are removed. After removal of the photoresist, in another aspect of this particular embodiment, a barrier layer may be deposited within the damascene structure opening and the MOM capacitor damascene opening, followed by depositing a metal within the damascene structure opening and the MOM capacitor damascene opening.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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Gibson Gerald W.
Gregor Richard W.
Sung Chun-Yung
Vitkavage Daniel J.
Yen Allen
Agere Systems Inc.
Nadav Ori
Thomas Tom
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