Damascene structure fabricated using a layer of...

Details Damascene structure fabricated using a layer of... Damascene structure fabricated using a layer of...

2002-11-08

2004-11-30

Lee, Hsien Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S762000, C257S774000, C438S637000, C438S638000, C438S700000, C438S788000

Reexamination Certificate

active

06825562

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The invention relates to semiconductor devices containing an interconnection structure comprising conductive wiring and conductive vias on a substrate and, more particularly, to a damascene structure that defines conductive paths and/or vias on a substrate and a method of fabricating same.
2. Description of the Background Art
The escalating requirements of density and performance associated with ultra large scale integrated circuits require responsive changes in interconnection technology. High density integrated circuits require planarized layers of interconnection paths and vias with minimal spacing between conductive paths. U.S. Pat. No. 5,262,354 discloses a three-step damascene technique for forming electrically conductive vias and interconnection lines on a substrate. Additionally, in U.S. Pat. No. 5,635,423, a simplified dual damascene process is disclosed for providing a multi-level metallization and interconnection structure wherein conductive vias and paths are formed simultaneously.
The dual damascene process taught in the '423 patent involves forming a first insulative layer (e.g., a layer of silicon oxide) upon a substrate and a silicon nitride etch stop layer upon the first insulative layer. A second insulative layer (e.g., silicon oxide) is formed on the etch stop layer and a first opening of about the size of the ultimate via is formed in the second insulative layer. Using a mask, a trench is formed in the second insulative layer while simultaneously forming a via in the etch stop and the first insulative layer. Subsequently, the mask is removed and a conductive material is simultaneously deposited in the via and trench.
Existing dual damascene processes utilize silicon dioxide as the insulator between the substrate and the conductive path, as well as between conductive paths. Also, the conventional dual damascene process uses silicon nitride as an etch stop to prevent distortion of the via size during the final etch step. The final etch step is generally used to create the via, as well as the interconnection trench, prior to filling the via and interconnection with a conductive material. The use of silicon nitride as an etch stop and a conventional photo-resist to define the trench in the second insulative layer can provide for very high selectivity for the etch process.
As integrated circuits have become more dense and switching speeds have increased, the materials used to fabricate the circuits and the conductive interconnections have been scrutinized. To reduce signal delay and cross-talk between conductive interconnections, insulative materials with low dielectric constants (e.g., k<3.5), known as “low k materials”, are becoming widely used, e.g., these materials are sold under the tradenames Flare 2.0, PAE-2, FPI, BCB, and the like. However, when organic or carbon-based low k materials (e.g., amorphous fluorinated carbon (a-C:F)) are used as the insulative layer within a single or dual damascene structure, the etch selectivity to conventional photoresist is poor when using an oxygen-based etch chemistry. In such situations, the dual damascene process sequence is conventionally modified to incorporate a “hard mask” fabricated of silicon dioxide or silicon nitride to define the trench. Such a silicon dioxide hard mask is not etched by the oxygen chemistry. Additionally, silicon nitride or silicon dioxide etch stop is also still used within the dual damascene structure. Consequently, the conventional low k dual damascene structure utilizes a material for the etch stop and hard mask that is distinct from the structure materials. Additionally, the hard mask and etch stop materials must be patterned using conventional photoresist techniques, necessitating numerous processing steps.
There has also been development in the use of plasma polymerized methylsilane (PPMS) material and other radiation sensitive organo-silicon materials as photoresists. The use of PPMS as a photoresist is disclosed in U.S. Pat. No. 5,439,780 issued Aug. 8, 1995 and herein incorporated by reference. Such radiation sensitive materials have not heretofore been used in conjunction with integrated circuit structures that include low k dielectric materials.
Therefore, there is a need in the art for a damascene structure and a method of fabricating such a structure that uses a photosensitive, silicon-based resist material which can function as a good hard-mask or etch-stop for patterning low k materials.
SUMMARY OF THE INVENTION
The invention overcomes the disadvantages associated with the prior art by providing a method of fabricating a damascene structure containing an insulative material having a low dielectric constant (e.g., k<3.5), hereinafter referred to as a low k material, using a silicon-based, organic material such as plasma polymerized methylsilane (PPMS) as a hard mask, etch stop and photoresist material. Both single and dual damascene structures benefit from such a use of silicon-based, organic material.
The process by which a dual damascene structure is fabricated in accordance with the invention begins by applying a film of low k material onto a semiconductor substrate; a layer of PPMS or other photosensitive silicon-based, resist material is deposited upon the low k film; and the resist is exposed to UV light according to a specific pattern for a via. When PPMS is used, the area of the PPMS layer exposed to the UV light is converted to plasma polymerized methylsilane oxide (PPMSO) and the unexposed area remains PPMS. The imaged layer is then developed by removing the PPMS using a chlorine (Cl
2
) or Cl
2
/HBr-based etchant to form a patterned layer of PPMSO. In this step, the underlying low k film is not affected by the etchants. Next, an additional low k film is deposited over the patterned PPMS layer. Thereafter, another layer of PPMS is uniformly deposited onto the second low k film. The second PPMS layer is exposed to UV light according to an interconnect pattern (i.e., the surface of the PPMS is masked), where the exposed area is converted to PPMSO and the unexposed area remains PPMS. The PPMS is etched with chlorine (Cl
2
) or Cl
2
/HBr-based etchant to define the interconnect pattern defining a trench.
The etch chemistry is then changed and the exposed layers of low k film are etched using an oxygen-based chemistry. The second layer of PPMSO behaves essentially as would a hard mask as it is not affected by the oxygen chemistry, while the first layer of PPMSO serves as an etch stop. The result of the etch is a dual damascene structure having at least one trench interconnected with a via. The dual damascene structure is then metallized and planarized to simultaneously form a conductive via and interconnection line. Planarization of the metallization is accomplished using, for example, chemical-mechanical polishing. The metallization is then conventionally passivated. Generally, passivation is accomplished using an H
2
-based chemistry to clean the surface oxide, followed by deposition of a layer of, for example, silicon-nitride, to prevent the copper surface from damage through the next series of steps needed to complete the next layer within the integrated circuit. For example, a cure process for a low k material may require a high temperature (400-450° C.) O
2
-based atmosphere that can severely oxidize the copper and increase the via/trench interface resistance among other detrimental effects. Additionally, low k material etch requires an O
2
-based chemistry that can also oxidize the exposed copper, if any.
The PPMSO has a very high resistance to oxygen plasma, with etch selectivity greater than 50 compared to the low k films being etched in an oxygen based chemistry. It is this high resistance to oxygen plasma that makes the PPMSO an excellent etch stop for etching low k materials when using an oxygen-based plasma.
To form a single damascene structure, a first layer of low k material is deposited upon a substrate and a layer of PPMS (or another silicon-based resist material) is deposited upon the laye

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