Damascene process for reduced feature size

Details Damascene process for reduced feature size Damascene process for reduced feature size

1997-02-13

1998-05-19

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257758, 257759, H01L 2358, H01L 2348, H01L 2352, H01L 2940

Patent

active

057539677

ABSTRACT:
Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.

REFERENCES:
patent: 4641420 (1987-02-01), Lee
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5117273 (1992-05-01), Stark et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5488242 (1996-01-01), Sunouchi et al.
patent: 5602423 (1997-02-01), Jain
"Method to produce sizes in openings in photo images smaller than lithographic minimum size," IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, p. 1328.
Kaanta et al., Dual Damascene: A ULSI Wiring Technology, Proceedings of the 8th International IEEE VLSI Multilevel Interconnection Conference, Jun. 11-12, 1991, pp. 144-152.

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