Damascene process

Details Damascene process Damascene process

1999-09-09

2001-02-20

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S672000, C438S702000

Reexamination Certificate

active

06191029

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a damascene process. More particularly, the present invention relates to a method of fabricating a metal interconnect for a semiconductor device.
2. Description of Related Art
Electromigration is the movement of the ions in a conductor (such as Cu) in response to the passage of current through it. These ions are moved “downstream” by the force of the “electron wind”. A positive divergence of the ionic flux leads to accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in an open-circuit failure of the conductor.
FIGS. 1A-1B
are schematic, cross-sectional views of a conventional Cu damascene process.
Referring to
FIG. 1A
, a dielectric layer
101
is deposited over a substrate
100
. The dielectric layer
101
is patterned to form an opening
102
exposing the substrate
100
. The opening
102
is filled with a conductive plug. The conductive plug conventionally comprises a conformal titanium nitride (TiN) layer
104
and a copper (Cu) layer
106
in the opening
102
.
Referring to
FIG. 1B
, a silicon nitride layer
108
and a plasma-enhanced oxide layer
110
arc sequentially deposited over the dielectric layer
101
. The plasma-enhanced oxide layer
110
is provided for the next damascene process.
Still referring to
FIG. 1B
, the Cu layer
106
directly contacts the overlying silicon nitride layer
108
in this damascene process. After performing a reliability test on this Cu layer
106
, it is found that ions of such a Cu layer
106
migrate in the direction of the overlying silicon nitride layer
108
, leading to accumulation of vacancies which form a void (not shown) in the Cu layer
106
. Such voids may ultimately grow to a size that results in an open-circuit failure of the Cu layer
106
.
SUMMARY OF THE INVENTION
The invention provides a damascene process. An opening is formed in a dielectric layer. The opening is filled with a conductive plug. An upper portion of the conductive plug is removed, thereby forming a concavity over the remaining conductive plug in the dielectric layer. The concavity is partially filled with a conformal top barrier layer in and over the dielectric layer. The concavity is over-filled with a spin-on-glass (SOG) layer over the top barrier layer. The portion of the spin-on-glass layer and the top barrier layer that lie over the dielectric layer is removed, thereby forming an electrical interconnect in the opening.
For one embodiment of this invention, the conductive plug comprises a conformal metal barrier layer and a Cu layer in the opening. Moreover, the top barrier layer can be made of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titaniumtungsten alloy (TiW), titanium-tungsten nitride (TiWN), or any combination thereof.
In this present invention, the top barrier layer increases the resistance of the damascene process to electromigration failure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5075763 (1991-12-01), Spitzer et al.
patent: 5229325 (1993-07-01), Park et al.
patent: 5888911 (1999-03-01), Ngo et al.
Sun, Y.; Radjy, N.; Cagnina, S.; 0.8 Micron Double Level Metal Technology with SOG Filled Tungsten Plug. 8th International IEEE VLSI Multilevel Interconnection Conference, 1991. pp. 51-57.

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