Damascene NiSi metal gate high-k transistor

Details Damascene NiSi metal gate high-k transistor Damascene NiSi metal gate high-k transistor

2000-12-07

2002-11-05

Everhart, C. (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S299000

Reexamination Certificate

active

06475874

ABSTRACT:

RELATED APPLICATIONS
The present invention contains subject matter similar to that disclosed in U.S. applications Ser. No. 09/691,181, filed on Oct. 19, 2000; U.S. application Ser. No. 09/734,189, filed on Dec. 12, 2000; U.S. application Ser. No. 09/734,185, filed on Dec. 12, 2000; U.S. application Ser. No. 09/734,186, filed on Dec. 12, 2000; and U.S. application Ser. No. 09/734,207, filed on Dec. 12, 2000.
FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing technology, more particularly to a method for fabricating field effect transistors by a low temperature silicide process.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by various efforts to decrease the size of device elements formed in integrated circuits (IC), and such efforts have contributed in increasing the density of circuit elements and device performance. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines.
Currently, the most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor device is a MOS (Metal Oxide Semiconductor) transistor. The principal elements of a typical MOS transistor generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped conductor to which an input signal is typically applied via a gate terminal. Heavily doped active regions, e.g., source/drain regions, are formed in the semiconductor substrate and are connected to source/drain terminals. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The gate electrode is generally separated from the semiconductor substrate by a dielectric layer, e.g., an oxide layer, to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
Conventional process steps for fabricating a typical MOS transistor are depicted in
FIGS. 1
to
8
. First, as depicted in FIG.
1
. an oxide layer is thermally grown on a semiconductor substrate
10
, i.e., typically silicon, and a conductive layer, typically polysilicon, is formed over the oxide layer. The oxide layer and conductive layer are patterned and etched to form gate dielectric
12
and gate electrode
14
, respectively. Then, as depicted in
FIG. 2
, impurity atoms, e.g., boron or phosphorus, are ion implanted into the surface of the silicon substrate
10
, by utilizing the gate electrode
14
as a mask, to form shallow source/drain regions
16
on the main surface of the silicon substrate
10
.
The ion implantation step is followed by an annealing step which normally involves a high temperature of 700° C. or higher to activate the implanted impurity atoms in the shallow source/drain regions
16
and to cure the damage caused by the physical impact to the crystal structure of the silicon substrate
10
when the impurity atoms are implanted thereto. Sidewall spacers
18
are then formed on the side surfaces of the gate dielectric
12
and gate electrode
14
, as depicted in FIG.
3
.
Subsequently, source/drain regions
20
are formed by ion implanting impurity atoms, e.g., boron or phosphorus, at the impurity implantation concentration and energy higher than those from the first annealing process, by utilizing the gate electrode
14
and the sidewall spacers
18
as a mask, as depicted in FIG.
4
. Once again, the annealing process is performed at a high temperature of 700° C. or higher to activate the implanted impurity atoms in the source/drain regions
20
and to cure the damage caused by the implantation impact.
As transistor dimensions approached one micron in diameter, conventional parameters resulted in intolerably increased resistance between the active region
20
and conductive interconnect lines formed subsequently to interconnect various device elements in the integrated circuit device. The principle way of reducing such contact resistance is by forming a metal silicide atop the source/drain regions
20
and the gate electrodes
14
prior to application of the conductive film for formation of the various conductive interconnect lines. The most common metal silicide materials are CoSi
2
and TiSi
2
.
As depicted in
FIG. 5
, a metal layer
22
is typically provided by first applying a thin layer of, for example, titanium, atop the wafer which contacts the source/drain regions
20
. Then, the wafer is subjected to one or more annealing steps at the temperature of 800° C. or higher. This causes the titanium layer
22
to selectively react with the silicon of the source/drain regions
20
and the gate electrodes
14
, thereby forming a metal silicide (TiSi
2
) layer
24
selectively on the source/drain regions
20
and the gate electrodes
14
. Such a process is referred to as a salicide (self-aligned silicide) process because the TiSi
2
layer
24
is formed only where the titanium material directly contacts the silicon source/drain regions
20
and the polycrystalline silicon gate electrode
14
. Following the formation of the silicide layer
24
, as depicted in
FIG. 7
, an interlayer dielectric film
26
is deposited over the entire surface of the substrate
10
, and an interconnect process is performed (not shown) to provide conductive paths by forming via holes through the interlayer dielectric
26
and filling the via holes with a conductive material, e.g., tungsten.
As the dimensions of the MOS transistor are further scaled down to submicron and nanometer dimensions, the thickness of the gate oxide is also scaled down accordingly. However, such excessively reduced thickness of the gate oxide causes charge carrier leakage by tunneling effect, thereby leading to faster degradation of the MOS transistor.
To solve this problem, a high k (dielectric constant) gate dielectric, e.g., ZrO
2
, HfO
2
, InO
2
, LaO
2
, TaO
2
, was introduced to replace the silicon oxide for submicron MOS devices. However, it has been also observed that the high k gate dielectric becomes thermally unstable during the high temperature process steps for fabrication of the MOS transistor. For example, as mentioned above, the source/drain region activation annealing steps in
FIGS. 2 and 4
and the silicidation step in
FIG. 6
are normally performed at a temperature of at least 700° C. or higher, or in some cases at a temperature of 1000° C. or higher. At such a high temperature, tantalum oxide (Ta
2
O
5
), another high k gate dielectric, is transformed from amorphous to crystalline, which causes charge carrier leakage. In addition, at such a high temperature, tantalum oxide undesirably interacts with the underlying silicon substrate or overlying polysilicon gate electrode of the MOS transistor.
To solve this problem, a metal gate electrode has been introduced to avoid the reaction between the high k gate dielectric and the polysilicon gate electrode during the high temperature processing steps. For example, as described in the U.S. Pat. No. 5,960,270 by Misra, et al. a metal deposition process was proposed to form a metal gate layer by depositing molybdenum, tungsten, tungsten silicide, nickel silicide, or titanium nitride. However, it has been also observed that the metal atoms from the gate electrode diffuse into the gate dielectric, thereby causing faster degradation of the high k gate dielectric, and both the high k gate dielectric and the metal gate electrode suffer structural stress from such high temperature process steps. Also, since the metal or metal silicide layer is deposited entirely over the semiconductor structure, it has been observed that it is difficult to controllably remove the unnecessary portions of the deposited metal or metal silicide layer to shape a metal or metal silicide gate due to the material unity.
Thus, there is a continuing need for improved methods that enable implementation of a reliable gate structure in submicron MOS transistors without the undesirable side effects and complic

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