Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-10-30
2000-06-20
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438618, 438624, 438633, 438629, 438675, 438637, H01L 214763
Patent
active
060777702
ABSTRACT:
A damascene manufacturing process capable of forming borderless via. The process includes the steps of forming a first trench in a first dielectric layer above a substrate, and then forming a conductive line within the first trench. Thereafter, a portion of the conductive line is removed to form a second trench within the first dielectric layer directly above the conductive line. Next, material is deposited into the second trench to form a cap layer. Subsequently, a second dielectric layer is deposited over the first dielectric layer, and then the second dielectric layer is patterned to form a via opening that exposes the cap layer. Next, the cap layer is removed to form a cavity region that exposes the conductive line. Finally, a plug is formed within the cavity region and the via opening such that the plug is electrically connected with the conductive line.
REFERENCES:
patent: 5935868 (1999-08-01), Fang et al.
patent: 5960316 (1999-09-01), Bai
patent: 5981373 (1999-11-01), Koyama
patent: 6015734 (2000-01-01), Huang et al.
patent: 6017813 (2000-01-01), Kuo
Bowers Charles
Nguyen Thanh
United Microelectronics Corp.
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