Damascene local interconnect process

Details Damascene local interconnect process Damascene local interconnect process

2000-03-07

2001-10-02

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S687000, C438S648000, C438S644000

Reexamination Certificate

active

06297144

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the manufacture of semiconductor integrated circuits. More particularly, it relates to a novel damascene interconnect process to avoid junction leakage.
2. Description of the Related Arts
Damascene is an interconnect fabrication process in which trenches for metal lines are etched in an interlevel dielectric (ILD) layer and filed with metal. The excess metal on the surface is removed and a planar structure with metal inlays in the dielectric layer is achieved. This process has several advantages over the traditional metal/ILD/planarization approach: (1) the surface at any time is totally flat; (2) the process eliminates the difficulty in filling small gaps between metal wires; and (3) it eliminates the difficulty in metal etching.
Damascene has been demonstrated in a number of applications. The most commonly applied process is the local interconnect. However, as shown in
FIG. 1
, once the process is applied in local interconnect
100
between different active areas, the edges
201
of isolation regions
200
result in large junction leakage. In semiconductor memory devices, the interconnect junction leakage become a critical issue for data storage. Thus, the aim of the present invention is to eliminate the disadvantages of the conventional approach while keeping the benefits of the damascene local interconnect.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a novel damancene local interconnect process to avoid junction leakage caused by the isolation edges.
To attain the above object, the present invention provide a process for forming a damascene local interconnect over a semiconductor substrate having first and second active areas which are isolated from each other, comprising the steps of: (a) forming a first dielectric layer over the substrate surface; (b) forming an interconnection in the upper level of the dielectric layer which spans over the first and second active areas; (c) forming a second dielectric layer over the first dielectric layer and the interconnection; (d) etching first and second contact holes adjacent to the opposite ends of the interconnection through the second and first dielectric layers, the first and second contact holes extending down to the first and second active areas respectively; and (e) filling the first and second contact holes with first and second conductive plugs respectively, wherein the interconnection thereby connects the first and second conductive plugs to couple the first and second active areas.
In accordance with the present invention, the step (b) is a typical damascene process which may comprise the steps of: forming an interconnection pattern in the upper level of the dielectric layer which spans over the first and second active areas; and filling the interconnection pattern with a conductive material such as tungsten. Instead of directly connecting active areas in the same level, the interconnection according to the present process is formed in the upper level of ILD layer and connects the conductive plugs to couple different active areas of the integrated circuit. As a result, the interconnection is exempted from contact with the isolation areas, thereby avoiding the interconnect junction leakage.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description which makes reference to the accompanying drawings.


REFERENCES:
patent: 5972789 (1999-10-01), Jeng et al.
patent: 6107189 (2000-08-01), Wald et al.
patent: 6191027 (2001-02-01), Omura
patent: 6207553 (2001-03-01), Buynoski et al.

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