Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-12-06
2004-02-03
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S157000
Reexamination Certificate
active
06686231
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices. The present invention has particular applicability to double-gate devices.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In several respects, the double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double-gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs. When there are two gates, the electric field generated by the drain is better screened from the source end of the channel. Also, two gates can control roughly twice as much current as a single gate, resulting in a stronger switching signal.
A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
DISCLOSURE OF THE INVENTION
Implementations consistent with the present invention may provide a method of forming a FinFET device that includes a high-k gate dielectric and a metal gate using a damascene process. A sacrificial oxide layer may be formed around a gate structure, which may be removed and replaced with a metal gate.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device including forming a fin structure on an insulator and forming a gate structure over a portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and replacing the gate structure within the sacrificial oxide layer with a metal gate. The sacrificial oxide layer may be removed.
According to another aspect of the invention, a method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. The method may also include forming a metal gate in the gate recess and removing the sacrificial oxide layer.
According to a further aspect of the invention, a method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include a dielectric cap. The method may also include forming a gate structure over a channel portion of the fin structure and forming a sacrificial oxide layer around the gate structure. The gate structure may be removed to define a gate recess within the sacrificial oxide layer. The method may also include removing the dielectric cap on the fin structure and forming a dielectric layer on the fin structure. A metal gate may be formed in the gate recess within the sacrificial oxide layer, and the sacrificial oxide layer may be removed.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.
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Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
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Co-pending U.S. Patent Application Ser. No. 10/645,577, filed Aug. 22, 2003, entitled: “Sacrificial Oxide Protection During Dummy Gate Removal in Damascene Gate Process in Semiconductor Devices”; Shibly S. Ahmed et al.; 28 pages.
Co-pending Application Ser. No. 10/320,536 entitled “Finfet Gate Formation Using Reverse Trim of Dummy Gate,” filed Dec. 17, 2002, 14 page specification, 11 sheets of drawings.
Ahmed Shibly S.
Wang Haihong
Yu Bin
Harrity & Snyder LLP
Wilczewski Mary
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