Damascene gate having protected shorting regions

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S413000, C438S592000

Reexamination Certificate

active

08039908

ABSTRACT:
The present invention relates generally to semiconductor devices and, more specifically, to damascene gates having protected shorting regions and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate with protected shorting regions, the method comprising: forming a damascene gate having: a gate dielectric atop a substrate; a gate conductor atop the gate dielectric; a conductive liner laterally adjacent the gate conductor; a spacer between the conductive liner and the substrate; and a first dielectric atop the gate conductor; removing a portion of the conductive liner; and depositing a second dielectric atop a remaining portion of the conductive liner, such that the second dielectric is laterally adjacent both the first dielectric and the gate.

REFERENCES:
patent: 5965462 (1999-10-01), Tan et al.
patent: 6054355 (2000-04-01), Inumiya et al.
patent: 6174762 (2001-01-01), Bronner et al.
patent: 6337278 (2002-01-01), Butler
patent: 6498096 (2002-12-01), Bruce et al.
patent: 6858483 (2005-02-01), Doczy et al.
patent: 7026689 (2006-04-01), Liaw
patent: 7316949 (2008-01-01), Doczy et al.
patent: 2006/0024940 (2006-02-01), Furukawa et al.

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