Damascene copper electroplating process with low-pressure...

Details Damascene copper electroplating process with low-pressure... Damascene copper electroplating process with low-pressure...

2002-01-29

2003-08-26

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S687000

Reexamination Certificate

active

06610600

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a damascene copper electroplating process with low-pressure pre-processing for fabricating interconnect structures on wafers, especially to a damascene copper electroplating process with low-pressure pre-processing for fabricating interconnect structures on wafers to reduce possible void and gap defects on a wafer.
2. Description of the Prior Art
The damascene copper electroplating process for fabricating interconnect structures on wafers has become popular in recent year. The current damascene copper electroplating process for fabricating interconnect structures on wafers is generally conducted at standard pressure (e.g. 1 atm. pressure) such that air is liable to remain in the plating solution and the trenches of the wafer. Therefore, the wafer may have void and gap defects after the damascene copper electroplating process.
As, shown in
FIG. 1
, when the wiring on the wafer
1
a
becomes thinner and the groove A on the wafer
1
a
will have a large aspect ratio (depth/width ratio). Subsequently, the problem of the void defect C and gap defect D becomes more serious.
FIG. 2
shows that a wafer
1
a
is dipped in a plating solution
3
a
under standard pressure
2
a
.
FIG. 3
shows that air bubbles B are formed on the surface of the wafer
1
a
when the wafer
1
a
is dipped in a plating solution
3
a
under standard pressure
2
a
.
FIG. 4
shows that void defect C and gap defect D on Cu-layer
4
a
are formed due to the air bubbles B after the damascene copper electroplating process is completed.
The current solution to above problem is to dispose the wafers
1
a
found with the void C and gap defect D. However, the wafers
1
a
are wasted
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a damascene copper electroplating process with low-pressure pre-processing for fabricating interconnect structures on wafers to reduce void and gap defects on the wafer.
In one aspect of the invention, the present invention provides a damascene copper electroplating apparatus with low-pressure pre-processing for fabricating interconnect structures on wafers. The damascene copper electroplating apparatus with low-pressure pre-processing comprises a hollow container, a venting tube, a venting control valve, a venting pump, an admission tube, an admission control valve, a transparent window, a plating solution inlet, a plating solution outlet, two control valves for controlling the flowing circuitry of the plating solution, a plating tank, and a sealing door.
In another aspect of the invention, the present invention provides a damascene copper electroplating process with low-pressure pre-processing for fabricating interconnect structures on wafers. The damascene copper electroplating process with low-pressure pre-processing comprises following steps: a. closing the two control valves to stop circulation of the plating solution; b. conveying a wafer to be plated on a predetermined location in a hollow container; c. venting the hollow container until the hollow container has a predetermined low pressure and then dipping the wafer into the plating solution; d. introducing external air until the pressure inside the hollow container has reached the standard value (e.g. 1 atm); e. opening the two control valves to re-circulate the plating solution; f. repeating steps a to e for next wafer.


REFERENCES:
patent: 4895633 (1990-01-01), Seto et al.
patent: 5368634 (1994-11-01), Hackett
patent: 6241869 (2001-06-01), Maeda

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