Damascene capacitors for integrated circuits

Details Damascene capacitors for integrated circuits Damascene capacitors for integrated circuits

1999-04-15

2001-08-07

Clark, Jhihan B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S770000, C257S764000, C257S763000

Reexamination Certificate

active

06271596

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a capacitor structure and method of making the capacitor for use in integrated circuits and a method for forming the structure.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) relates to electronic devices consisting of cells which can retain information only for a limited time before they must be read and refreshed at periodic intervals. A typical DRAM cell consists of at least one transistor and a storage capacitor. In general, the integrated circuit used for DRAMs consists of metal oxide semiconductor (MOS) and particularly complementary MOS structures (CMOS) as the transistor component. Recently, the capacity of such DRAM structures has evolved from one megabit to on the order of one gigabit. This increase in memory has required the evolution of gate feature sizes on the order of 1.25 microns down to on the order of 0.25 microns or smaller. As the DRAM capacity requirements are increased, the requirements placed on the capacitors are increased as well. Not only is there a requirement for increased capacitance, there is also a requirement to increased capacitance density. Accordingly, development efforts have been focused on materials and structures to meet this need. To minimize interconnection resistance and to maximize the use of valuable chip area, advanced VLSI and ULSI logic integrated semiconductor circuits use multi-level wiring line structures for interconnecting regions within the devices and for interconnecting one or more devices within the integrated circuit. Multi-level metallization provides greater flexibility in circuit design, a reduction in die size and, thereby, a reduction in chip cost. In fabricating such structures, the conventional approach is to form lower level wiring lines (or interconnect structures) and then form one or more upper level wiring lines interconnected with the first level wiring lines. A first level interconnect structure may be in contact with the doped region within the substrate of an integrated circuit device (for example the source or drain of a typical MOSFET). One or more interconnections are typically formed between the first level interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device. This is accomplished through the second and subsequent levels of wiring lines. An example of the multi-layer interconnect structure used in conventional VLSI and ULSI structures can be seen in FIG.
1
. Conductive vias, shown generally at
101
are used to make the connection from one level to another. As is shown in
FIG. 1
, metal layer M-
1
at the first level is connected to the source (S) formed in the substrate layer of the integrated circuit. This metal layer M-
1
is used to make electrical connections at level one as well as at higher levels using the via structure as shown.
An embedded DRAM structure adds integrated capacitors to the logic transistors to add high density memory cells to the circuit. These integrated capacitors can be connected to the source metallization of the MOS device to form the memory cell. Conventional DRAM capacitors often have a layer of polysilicon as the bottom electrode; a layer of silicon dioxide or silicon nitride as the insulator; and a top metal layer forming the top electrode. Such a structure is generally not compatible with embedded technology because of the added complexity of the poly-Si capacitors and the high temperatures required to grow the silicon oxide
itride layer. For example, the aluminum metal layers used as interconnects in the multi-layer structure can be adversely affected by the relatively high temperatures used in the deposition of polysilicon. Furthermore, the use of polysilicon as an electrode can have deleterious affects on the electrical characteristics of the device. It is known to use tantalum pentoxide as the dielectric of the capacitor because of its a higher dielectric constant compared to silicon dioxide or silicon nitride. During the chemical vapor deposition used to form the tantalum pentoxide, a layer of silicon dioxide is formed generally between the polysilicon layer and the tantalum pentoxide layer. This layer of silicon dioxide is not desired, as it tends to adversely impact the capacitance of the capacitor. Accordingly, there is a need for a capacitor structure in DRAM's which avoids the use of polysilicon electrodes.
FIG. 2
shows the capacitor structure disclosed in U.S. Pat. No. 5,576,240 to Radosevich et al, the disclosure of which is specifically incorporated by reference herein. In the structure shown in
FIG. 2
, a capacitor has a lower plate
201
with a layer of dielectric
202
and a top plate
203
in the trench structure as shown. While the structure shown in
FIG. 2
has certain advantages compared to planar-type storage capacitors, applicants have recognized that this structure may not lend itself well to multi-layer reduced feature size ULSI fabrication techniques. In particular, planarization plays an important role in the fabrication of multi-layer integrated circuits. To this end, during the process of circuit fabrication, various growth and deposition techniques used to form insulating and conducting layers can result in an increasingly non-planar structure which presents two major problems. The first problem is one of maintaining step coverage without breaks in the continuity of fine line structures. The second problem is a reduction in the optical resolution and therefore reduction in the ability to image fine-line patterns over the wafer structure. Accordingly, polishing techniques are used to maintain planarity at each level in a multi-level structure. One technique which has become widely embraced for planarization is chemical mechanical polishing (CMP). Such a polishing step would be utilized after the fabrication of the capacitor shown at
FIG. 2
in order to maintain a planar topology. After the fabrication of the capacitor
204
, a CMP or other planarization step would be employed and subsequent deposition of metal and dielectric layers for the next level of the multi-level structure would be carried out. However, the layers shown as
201
,
202
and
203
which form the layers of the capacitor are relatively thin. Applicants recognize that chemical mechanical polishing could result in the shorting of layers
201
and
203
. Thus, applicants have determined that chemical mechanical polishing technique which is clearly desired in the fabrication of multi-layer integrated circuits may not be compatible with a capacitor structure as shown in FIG.
2
.
What is needed, therefore, is a capacitor structure which improves the capacitance density while being readily adaptable to standard/low temperature processing and planarization techniques.
SUMMARY OF THE INVENTION
The present invention relates to a conductive plug capacitor and method of manufacture thereof for use in multi-level integrated circuit structures. In an illustrative embodiment, a conductive plug is formed in a window in a dielectric layer and thereafter a cavity is formed in the plug. This cavity may serve as the lower plate of the capacitor, with a layer of dielectric deposited in the cavity and a top conductive layer (e.g., metal) disposed thereon serving as the upper plate. During the fabrication of the capacitor, chemical mechanical polishing is done after the formation of the conductive plug. Thereafter, the cavity is etched in the plug with the deposition of the dielectric and top plate following. The CMP process results in a substantially planarized dielectric and tungsten plug, thereby making the capacitor fabrication sequence compatible with multi-layer fabrication techniques.


REFERENCES:
patent: 4912540 (1990-03-01), Sander et al.
patent: 5244837 (1993-09-01), Dennison
patent: 5576240 (1996-11-01), Radosevich et al.
patent: 5654581 (1997-08-01), Radosevich et al.
patent: 5677563 (1997-10-01), Cronin et al.
patent: 5753948 (1998-05-01), Nguyen
patent: 5801094 (1998-09-01), Yew et al.
patent: 5972789 (1999-10-01), Jeng et

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