Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-01
2004-06-01
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S288000, C257S304000, C257S305000, C438S386000
Reexamination Certificate
active
06744090
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a semiconductor device with a capacitor and an interconnection formed by a damascene process.
DESCRIPTION OF RELATED ART
Logic elements become more highly integrated and their processing speed gets faster and faster, as transistors become finer. In response to the integration of transistors, interconnections have become finer and the number of interconnection layers is increasing dramatically. As a result, the problem of interconnection delay caused by miniaturization is intensified in a high-speed and highly integrated device and is a factor that limits the speed of the device.
In this circumstance, a method is needed of forming an interconnection using copper with a lower specific resistance and higher electromigration (EM) property than an aluminum alloy, a material conventionally used for the interconnections of a large scale integration (LSI).
However, since copper is not easily etched in a conventional dry etching method which has been used for forming an aluminum interconnection, and it is easily oxidized during the process, a damascene process is used to form a copper interconnection.
The damascene process is entirely different from the conventional processing series of aluminum deposition, reactive ion etching (RIE) and deposition of insulation material and planarization. That is, the damascene process is a filling process composed of forming an interconnection trench and an access hole on an insulation layer, filling them with copper and then planarizing using a chemical mechanical polishing (CMP) method.
There is a single damascene process which forms an interconnection trench and access plug separately, and a dual damascene process which forms the access plug and interconnection trench concurrently. In the case of the dual damascene process, since the access plug and interconnection trench are formed concurrently, the aspect ratio is higher than with the single damascene process, but the dual damascene process is commonly used in order to lower processing cost.
The dual damascene process consists of a sequence of forming an access hole and an interconnection trench, forming a barrier metal, filling the access hole and interconnection trench with copper, and polishing the copper and the barrier metal using a CMP method.
Meanwhile, a capacitor, a passive element, is formed during the process of the semiconductor device fabrication to form various logic elements. As an example, in a micro processor unit (MPU), a decoupling capacitor is formed; and in a system on a chip (SOC) and a radio frequency (RF) element, a coupling and bypass capacitor is formed for impedance matching between the blocks, while in an analog to digital (AD) converter or a digital to analog (DA) converter, a capacitor array is formed.
To form these capacitors, a junction capacitor using a silicon junction or a metal/insulator/metal (MIM) capacitor of aluminum/silicon nitride layer/aluminum (Al/SiN/Al) that is formed by using a silicon nitride (SiN) layer as a dielectric layer which is deposited in a plasma enhanced chemical vapor deposition (PECVD) method in a conventional aluminum interconnection technology, have been formed so far
However, as operational frequency and a number of bits of a converter increase, a capacitor with. higher capacity is needed. For instance, in the case of a central processing unit (CPU) that operates at 1 GHz, 400 nF of capacitor capacity is needed for decoupling. Here, if the thickness (Toxeq) of an effective oxide layer is 1 nm, the capacitor is 34.5 nF/mm
2
, and an area of 11.6 mm
2
is needed for 400 nF. The. dielectric constant of a 1000 ÅSiN layer deposited in a PECVD method is 7, the thickness (Toxeq) of an effective oxide layer is around 56 nm, and as the capacitance is 0.62 nF/mm
2
, a capacitor with an area of 645 mm
2
is needed for 400 nF, which cannot be realized in the conventional manufacturing process of a semiconductor chip.
Consequently, a structure that can increase the capacity of a capacitor without increasing the processing steps and the area of the device is required.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device that forms a capacitor and a metal interconnection in the same level of a layer by using a damascene process method, and a semiconductor device formed by the method.
In accordance with an embodiment of the present invention, there is provided a method for forming a semiconductor device, including steps of a) forming an insulation layer in a capacitor region and a metal interconnection region on a substrate; b) forming a metal interconnection in the metal interconnection region of the insulation layer by performing a dual damascene process; and c) forming a capacitor in the capacitor region of the insulation layer such that the capacitor is in a same level as the metal interconnection in the insulation layer.
In accordance with another embodiment of the present invention, there is provided a method for fabricating a semiconductor device, comprising steps of a) forming an insulation layer including first and second insulation layers in a capacitor region and a metal interconnection region on a substrate formed with a lower conductive layer; b) forming an interconnection trench in the metal interconnection region, a first trench in the capacitor region and a via hole connected to the lower conductive layer by selectively etching the insulation layer; c) forming a copper interconnection, a first copper interconnection and a via contact plug by, forming a first copper layer in the interconnection trench, the access hole and the first trench and planarizing a resulting structure; d) forming a second trench by selectively etching the second insulation layer in the capacitor region; e) forming a capacitor composed of a first electrode, a dielectric layer and a second electrode on side and bottom surfaces of the second trench; and f) forming a second copper interconnection by forming a second copper layer on the capacitor and planarizing the second cooper layer.
In accordance with yet another embodiment of the present invention, there is provided a method for fabricating a semiconductor device, comprising steps of a) forming an insulation layer including first and second insulation layers in a metal interconnection region and a capacitor region on a substrate formed with a lower conductive layer; b) forming an interconnection trench in the metal interconnection region, a first trench in the capacitor region and a via hole by selectively etching the insulation layer; c) forming a copper interconnection, a via contact plug and a first copper interconnection by forming a first barrier metal and a first copper layer in the interconnection trench, the via hole and the first trench and planarizing a resulting structure; d) forming a second trench by selectively etching the second insulation layer around the first copper interconnection in the capacitor region; e) forming a third trench in the first barrier metal by selectively etching the first copper interconnection; f) forming a capacitor composed of a first electrode, a dielectric layer and a second electrode on side and bottom surfaces of the second and third trenches; and g) forming a second copper interconnection by forming a second copper layer on the capacitor and planarizing the second copper layer.
In accordance with a further embodiment of the present invention, there is provided a semiconductor device, comprising a substrate; an insulation layer formed in a metal interconnection region and a capacitor region on the substrate; a metal interconnection in the insulation layer of the metal interconnection region; and a capacitor formed in the capacitor region of the insulation layer in a same level as the metal interconnection.
The present invention forms a three-dimensional capacitor on a damascene pattern by maintaining the conventional process in a damascene process.
Flynn Nathan J.
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Wilson Scott R
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